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5 compiled memory
contents overview ....................................................................................................................... ....... 5-1 compiled memory naming convention................................................................................ 5-1 characteristics for timing and power................................................................................... 5-2 built-in self test and built-in redundancy-analysis ............................................................ 5-4 compiled memory selection guide...................................................................................... 5-5 high-density compiled memory spsram_hd high-density single-port synchronous sram ....................................... 5-9 spsrambw_hd high-density single-port synchronous sram with bit-write................. 5-24 spsramr_hd high-density single-port synchronous sram with redundancy .......... 5-39 dpsram_hd high-density dual-port synchronous sram.......................................... 5-49 dpsrambw_hd high-density dual-port synchronous sram with bit-write ................... 5-60 sparam_hd high-density single-port asynchronous sram ..................................... 5-71 sparambw_hd high-density single-port asynchronous sram with bit-write ............... 5-86 drom_hd high-density synchronous diffusion programmable rom .................... 5-102 mrom_hd high-density synchronous metal-2 programmable rom ...................... 5-114 arfram_hd high-density multi-port asynchronous register file.............................. 5-126 fifo_hd high-density synchronous first-in first-out memory............................ 5-146 cam_hd high-density synchronous content addressable memory .................... 5-159 low-power compiled memory spsram_lp low-power single-port synchronous sram .......................................... 5-172 spsrambw_lp low power single-port synchronous sram with bit-write.................... 5-182 dpsram_lp low-power dual-port synchronous sram ............................................ 5-193 dpsrambw_lp low-power dual-port synchronous sram with bit-write ...................... 5-204 sparam_lp low-power single-port asynchronous sram ........................................ 5-216 sparambw_lp low-power single-port asynchronous sram with bit-write.................. 5-227
compiled memory overview samsung asic 5-1 std130 overview this section is an overview of the std130 compiled memory. in std130 compiled memories provide application-speci? memory solution high-density and low-power application. that is, two different compiled memory libraries are available in std130: std130-hd(high-density) and std130-lp(low-power) . the high-density compiled memories are suitable for high integration application. the low-power compiled memories are suitable for portable applications. each of these memory types may be customized to satisfy the speci? circuit requirements. each memory uses state-of-the-art design architecture techniques. the ?al memory block is implemented as stand-alone, pitch-matched and customized leafcells. the compiled memory is fully generated by a user-con?urable compiler, called memory compiler. the user de?es the memory related speci?ations such as word depth, bit per word, and column mux type. the compiler then produces any or all of the following items: ? complete functional model for simulation ? tabular model for timing and power characteristics ? automatic generated datasheet including all information for speci? memory con?uration ? full gds and schematic netlist for layout veri?ation ? phantom cell to use in chip-level ?or planning and layout additional information about memory compilers can be obtained from your local samsung and design center or samsungs worldwide headquarters. compiled memory naming convention in this chapter, we describe the naming convention of memory. the memory name, figure 5-1 consists of the following convention. figure 5-1. compiled memory naming convention the ?st string, memory_code ? is the name of memory type. in std130 compiled memory types are as follows: spsram : single-port synchronous sram spsrambw : single-port synchronous sram with bit-write ? spsramr : single-port synchronous sram with redundancy dpsram : dual-port synchronous sram ? dpsrambw : dual-port synchronous sram with bit-write sparam : single-port asynchronous sram ? sparambw : single-port asynchronous sram with bit-write drom : synchronous diffusion-programmable rom mrom : synchronous metal2-programmable rom ? arfram : multi-port asynchronous register file fifo : synchronous first-in first-out memory ? cam : synchronous content addressable memory ?emory_name?= [memory_code]_[appl_code]_[procs_code]_[opt_code]_[con?_code]
characteristics for timing and power compiled memory std130 5-2 samsung asic the second string, appl_code ? means the speci? application to suitably support the compiled memory and the application code is one of hd(high-density) and lp(low-power). the third string, procs_code ? represents the process and the process code is one of generic process and low-power process(l). in case of generic process, you don? have to specify procs_code ? if there is no process code, it means that the memory is developed under generic process. if the process code is set to l, it means that the memory is under low-power process. the fourth string, opt_code ? represents the number of read and write ports for multi-port memory and the option code is composed of the following convention: ?pt_code?= rw currently this ?ld is only used for arfram, where n is the total number of read ports (1~2) and m is the total number of write ports (1~2). the last string, con?_code ? represents the con?uration of the memory to be speci?d. this con?uration code is composed of the following convention: ?on?_code?= x m b where, word is the word depth, bpw is bit per word, ymux is the available column mux type and bank is the number of bank used. for example, spsram_hd_1024x32m16b2 refers to a high-density single-port synchronous sram with 1024 words, 32 bits, 16 column mux and 2 bank under generic process. second, ?rfram_hd_1r2w_32x32m2?refers to a high-density three-port (1 read/2 write) asynchronous register ?e with 32 word, 32 bits and 2 column mux under generic process. spsram_lpl_1024x32m16?refers to a low-power single-port synchronous sram with 1024 words, 32 bits 16 column mux under low-power process. characteristics for timing and power std130 compiled memories are fully optimized for 1.8v 0.15v supply voltage. compiled memory in this section has been characterized using typical-process at 25 degree and 1.8v supply. the worst-case and best-case parameters can be found by using the derating factor calculated from the following equation: t wc (t bc ) = k p_local k v_local k t_local t nom where, t wc is a worst-case propagation delay t bc is a best-case propagation delay t nom is a typical-case propagation delay characterized under typical-process, 25 degree and 1.8v supply k p_local is a local process derating factor corresponding to each memory type. k v_local is a local voltage derating factor corresponding to each memory type. k t_local is a local temperature derating factor that varies by memory type. note that k p_local , k v_local and k t_local are only used in compiled memories.
compiled memory characteristics for timing and power samsung asic 5-3 std130 a two-dimensional timing characteristics table look-up model has been adopted to yield more accuracy. based on the combination of input slopes and output loads, the propagation delay is measured from the input crossing 50% v dd to the output crossing 50% v dd . the timing values reported in the tables are also taken from the same voltage level as the switching characteristics with 0.2ns for input slope and 10sl (standard load) for output load. the power consumption for read and write modes is measured for on input slope of 0.2ns, an output load of 10sl and an input switching activity factor of 0.5. the total power consumption can be calculated by the following equation: p total = ((sa read p read ) + (sa write p write )) f max where, p total is the total power consumption in microwatts p read is the read power consumption in microwatts per mhz p write is the write power consumption in microwatts per mhz sa read is the read access ratio on every cycle sa write is the write access ratio on every cycle f max is the ram clock frequency in mhz. the value of sa read or sa write is between 0 and 1. however, the sum of sa read and sa write must be less than or equal to 1. the power values reported in the tables are also taken from 50% switching activity, sa=0.5. for compiled memory, the read power consumption, the write power consumption and the standby power consumption are available. the standby power consumption is measured on the condition that csn (chip select negative) disabled and for other signals in their normal operating mode except that oen (output enable negative) is held low. if any of the signals are not active during standby mode, the standby power is near zero and only static leakage power consumed. in dual-port memories, the power consumption is measured with only one port active and the other port isolated.
built-in self test and built-in redundancy-analysis compiled memory std130 5-4 samsung asic built-in self test and built-in redundancy-analysis samsung provides engineering design services to support built-in self-test (bist) and built-in redundancy analysis (bira) for compiled memories. bist is the recommended test solution for compiled memories. samsung bist circuits are designed to detect a complete range of fault types such as stuck-at faults, transition faults, coupling faults, and address macrocells of the same or different types exist together in a circuit, samsung supports the bist for all to the memories as a single architecture. bira design services is also provided to test redundancy rams with testers. bira tests a sram and generates fail information after redundancy analysis. the fail information gathered by logic tester is automatically processed and transferred to the laser repair machine. for multiple redundancy rams, samsung bira architecture has an integration module to support parallel testing, minimum test pin usage, and optimize logic tester interface. for more detailed information regarding to the bist and bira, please contact your local samsung and design center or samsungs worldwide headquarters.
compiled memory selection guide for compiled memory samsung asic 5-5 std130 selection guide for compiled memory high-density compiled memory high-density description spsram_hd - high-density single-port synchronous static ram - duty-free clock operation - zero hold time for address, data-in and other control pins - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) spsrambw_hd - high-density single-port synchronous static ram - bit-write feature available - duty-free clock operation - zero hold time for address, data-in and other control pins - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) spsramr_hd - high-density single-port synchronous static ram with redundancy - bit-write feature available - duty-free clock operation - zero hold time for address, data-in and other control pins - row-only redundancy available - failure analysis by bira and laser repair - flexible aspect ratio (ymux = 8, 16, 32) dpsram_hd - high-density dual-port synchronous static ram - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 4, 8, 16, 32) dpsrambw_hd - high-density dual-port synchronous static ram - bit-write feature available - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 4, 8, 16, 32) sparam_hd - high-density single-port asynchronous static ram - synchronous write operation / asynchronous read operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32) sparambw_hd - high-density single-port asynchronous static ram - bit-write feature available - synchronous write operation / asynchronous read operation - dual bank available - flexible aspect ratio (ymux = 4, 8, 16, 32)
selection guide for compiled memory compiled memory std130 5-6 samsung asic drom_hd - high-density synchronous diffusion programmable rom - diffusion programmable coded - duty-free clock operation - zero hold time for address and other control pins - dual bank available - flexible aspect ratio (ymux = 8, 16, 32) mrom_hd - high-density synchronous metal-2 programmable rom - metal-2 programmable coded - duty-free clock operation - zero hold time for address and other control pins - dual bank available - flexible aspect ratio (ymux = 8, 16, 32) arfram_hd - high-density multi-port asynchronous register file - synchronous write operation / asynchronous read operation - 1-to-2 write ports / 1-to-2 read ports - flexible aspect ratio (ymux = 2, 4, 8) fifo_hd - high-density synchronous first-in first-out memory - duty-free clock operation - reset and re-transmit operation available - flexible aspect ratio (ymux = 2, 4, 8, 16) cam_hd - high-density synchronous binary content addressable memory - duty-free clock operation - single cycle compare operation - built-in priority address encoder available - global hit/miss handling high-density description
compiled memory selection guide for compiled memory samsung asic 5-7 std130 low-power compiled memory low-power description spsram_lp - low-power single-port synchronous static ram - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 2, 4, 8, 16) spsrambw_lp - low-power single-port synchronous static ram - bit-write feature available - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 2, 4, 8, 16) dpsram_lp - low-power dual-port synchronous static ram - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 2, 4, 8, 16) dpsrambw_lp - low-power dual-port synchronous static ram - bit-write feature available - duty-free clock operation - zero hold time for address, data-in and other control pins - flexible aspect ratio (ymux = 2, 4, 8, 16) sparam_lp - low-power single-port asynchronous static ram - synchronous write operation / asynchronous read operation - flexible aspect ratio (ymux = 2, 4, 8, 16) sparambw_lp - low-power single-port asynchronous static ram - bit-write feature available - synchronous write operation / asynchronous read operation - flexible aspect ratio (ymux = 2, 4, 8, 16)
std130 5-8 samsung asic note
samsung asic 5-9 std130 spsram_hd high-density single-port synchronous static ram logic symbol function description spsram_hd is a single-port synchronous static ram which is provided as a compiler. spsram_hd is intended for use in high-density applications. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data on di[] is written into the memory location speci?d on a[]. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. spsram_hd function table parameter description spsram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba). ck csn wen oen a di dout comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) l l l valid valid dout(t-1) write cycle l h l valid x mem(a) read cycle ck csn wen oen a [m?:0] spsram_hd_xmb dout [b?:0] di [b?:0] notes: 1. words(w) is the number of words. 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. 4. banks(ba) is the number of banks. 5. m = ? log 2 w ? features suitable for high-density application separated data i/o synchronous operation duty-free clock cycle asynchronous tri-state output latched inputs and outputs automatic power-down zero standby current zero hold time low noise output optimization flexible aspect ratio dual-bank scheme available up to 512k bits capacity up to 32k number of words up to 128 number of bits per word
std130 5-10 samsung asic spsram_hd high-density single-port synchronous static ram pin descriptions pin capacitance unit: [sl] note: each pin? capacitance is exactly same regardless of available mux types for same bank. parameters ymux(y) = 4 ymux(y) = 8 ymux(y) = 16 ymux(y) = 32 words (w) ba = 1 min 32 64 128 256 max 2048 4096 8192 16384 step 16 32 64 128 ba = 2 min 64 128 256 512 max 4096 8192 16384 32768 step 32 64 128 256 bpw (b) min 1 1 1 1 max 128 64 32 16 step 1 1 1 1 name type description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writ- ing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di [ ] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout 10.83 6.39 4.45 4.45 4.45 4.45 16.06
samsung asic 5-11 std130 spsram_hd high-density single-port synchronous static ram block diagrams spsram_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from spsram_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the middle-edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. <1-bank architecture> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vdd vss vdd vss vdd vss vdd vss dout[b-1:b/2] di[b-1:b/2] a[m-1:0] wen oen csn ck dout[b/2-1:0] di[b/2-1:0]
std130 5-12 samsung asic spsram_hd high-density single-port synchronous static ram application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in spsram_hd is permitted only for metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsram_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver vss vdd vdd vss vdd vss vss vdd vdd vss vdd vss dout[b/2-1:0] di[b/2-1:0] a[m-1:0] wen oen csn ck dout[b-1:b/2] di[b-1:b/2]
samsung asic 5-13 std130 spsram_hd high-density single-port synchronous static ram characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckh clock pulse width high t ckl clock pulse width low t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations. de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
std130 5-14 samsung asic spsram_hd high-density single-port synchronous static ram reference table * for ymux=4 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 128 256 256 512 512 768 768 bpw 32 32 48 48 64 64 80 80 ba 12121212 timing (ns) t cyc 1.94 1.95 2.00 1.98 2.09 2.04 2.18 2.11 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.69 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.38 0.39 0.37 0.37 0.37 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.54 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.61 1.61 1.66 1.65 1.76 1.71 1.84 1.77 t da 1.15 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.10 0.10 0.11 0.11 0.12 0.12 0.13 0.13 t zd 0.13 0.13 0.14 0.14 0.16 0.16 0.17 0.17 t od 0.59 0.59 0.61 0.61 0.63 0.63 0.65 0.65 power ( w/mhz) power_read 144.92 160.26 202.35 219.94 263.87 283.04 328.57 351.72 power_write 151.91 166.62 218.63 232.05 300.52 306.10 391.86 388.47 power_standby 47.65 55.85 65.40 75.64 83.52 96.39 101.11 117.03 area ( m) width 494.08 579.84 686.08 814.72 878.08 1049.60 1090.68 1305.08 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
samsung asic 5-15 std130 spsram_hd high-density single-port synchronous static ram reference table * for ymux=4 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.26 2.17 2.45 2.26 2.48 2.35 2.60 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.69 0.69 0.68 0.69 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.36 0.36 0.35 0.35 0.35 0.35 0.35 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.92 1.83 2.12 1.92 2.15 2.01 2.26 t da 1.44 1.32 1.63 1.40 1.65 1.47 1.70 t dz 0.13 0.13 0.14 0.14 0.14 0.14 0.14 t zd 0.18 0.18 0.19 0.19 0.19 0.19 0.19 t od 0.67 0.67 0.70 0.70 0.72 0.72 0.72 power ( w/mhz) power_read 392.52 419.57 472.31 493.91 537.70 570.89 623.00 power_write 491.61 474.42 633.34 582.60 780.80 700.40 848.20 power_standby 119.50 139.17 137.86 163.08 156.20 187.73 203.00 area ( m) width 1282.68 1539.96 1474.68 1774.84 1666.68 2009.72 2009.72 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
std130 5-16 samsung asic spsram_hd high-density single-port synchronous static ram reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 256 512 512 1024 1024 1536 1536 bpw 16 16 24 24 32 32 40 40 ba 12121212 timing (ns) t cyc 1.95 1.95 2.00 1.99 2.09 2.05 2.18 2.11 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.39 0.39 0.38 0.39 0.38 0.38 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.53 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.61 1.61 1.67 1.65 1.76 1.71 1.84 1.77 t da 1.16 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.10 0.10 0.11 0.11 0.11 0.11 t zd 0.12 0.12 0.13 0.13 0.14 0.14 0.15 0.15 t od 0.57 0.57 0.59 0.59 0.60 0.60 0.62 0.62 power ( w/mhz) power_read 116.65 130.11 160.09 174.55 207.92 222.17 258.88 275.91 power_write 124.89 139.54 175.19 189.93 234.88 245.91 301.63 308.92 power_standby 31.36 39.18 40.98 50.50 51.02 62.46 60.13 73.90 area ( m) width 494.08 536.96 686.08 750.40 878.08 963.84 1090.68 1197.88 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
samsung asic 5-17 std130 spsram_hd high-density single-port synchronous static ram reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.26 2.17 2.46 2.26 2.48 2.35 2.60 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.69 0.68 0.69 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.37 0.37 0.37 0.37 0.36 0.36 0.36 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.92 1.83 2.12 1.92 2.15 2.01 2.26 t da 1.44 1.32 1.63 1.40 1.65 1.48 1.70 t dz 0.12 0.12 0.12 0.12 0.13 0.13 0.13 t zd 0.16 0.16 0.17 0.16 017 0.17 0.18 t od 0.64 0.64 0.66 0.66 0.67 0.67 0.67 power ( w/mhz) power_read 308.45 327.15 373.81 383.06 424.30 440.75 483.30 power_write 371.36 371.15 467.15 447.76 560.80 529.25 615.70 power_standby 70.23 86.72 80.29 100.40 90.43 114.43 123.10 area ( m) width 1282.68 1411.32 1474.68 1624.76 1666.68 1838.20 1838.20 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
std130 5-18 samsung asic spsram_hd high-density single-port synchronous static ram reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 512 1024 1024 2048 2048 3072 3072 bpw 8 8 12 12 16 16 20 20 ba 12121212 timing (ns) t cyc 1.96 1.98 2.02 2.02 2.11 2.08 2.20 2.14 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.40 0.40 0.39 0.39 0.39 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.53 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.63 1.64 1.68 1.67 1.77 1.73 1.86 1.80 t da 1.16 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.10 0.10 0.10 0.10 0.11 0.11 t zd 0.12 0.12 0.13 0.13 0.14 0.14 0.14 0.14 t od 0.57 0.57 0.58 0.58 0.59 0.59 0.61 0.61 power ( w/mhz) power_read 88.02 101.27 117.15 131.22 150.71 164.10 186.90 202.61 power_write 91.51 106.57 123.77 139.65 162.73 176.74 206.39 219.79 power_standby 24.43 31.99 30.59 39.64 37.13 47.78 42.65 54.99 area ( m) width 494.08 515.52 686.08 718.24 878.08 920.96 1090.68 1144.28 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
samsung asic 5-19 std130 spsram_hd high-density single-port synchronous static ram reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.27 2.20 2.47 2.29 2.50 2.38 2.63 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.69 0.68 0.69 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.38 0.38 0.38 0.38 0.37 0.37 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.94 1.86 2.14 1.95 2.16 2.04 2.29 t da 1.44 1.32 1.63 1.40 1.65 1.48 1.70 t dz 0.11 0.11 0.12 0.12 0.12 0.12 0.12 t zd 0.15 0.15 0.15 0.15 0.16 0.16 0.16 t od 0.62 0.62 0.64 0.64 0.65 0.65 0.65 power ( w/mhz) power_read 222.00 238.66 272.75 278.62 308.80 320.01 358.60 power_write 251.47 261.65 314.38 311.83 371.00 365.32 421.20 power_standby 49.29 63.82 55.88 73.06 62.58 82.42 87.79 area ( m) width 1282.68 1347.00 1474.68 1549.72 1666.68 1752.44 1752.44 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
std130 5-20 samsung asic spsram_hd high-density single-port synchronous static ram reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 2048 2048 4096 4096 6144 6144 bpw 4466881010 ba 12121212 timing (ns) t cyc 1.99 2.03 2.05 2.07 2.14 2.13 2.23 2.20 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.41 0.41 0.40 0.40 0.39 0.39 0.39 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.53 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.65 1.69 1.70 1.73 1.80 1.79 1.89 1.85 t da 1.16 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.09 0.09 0.10 0.10 0.10 0.10 t zd 0.12 0.12 0.12 0.12 0.13 0.13 0.14 0.14 t od 0.57 0.57 0.58 0.58 0.59 0.59 0.60 0.60 power ( w/mhz) power_read 73.69 87.03 95.57 109.80 121.91 135.38 150.87 165.93 power_write 74.35 89.81 97.31 113.99 125.56 141.40 157.38 173.46 power_standby 20.44 27.86 24.61 33.43 29.17 39.39 32.37 43.74 area ( m) width 494.08 504.80 686.08 702.16 878.08 899.52 1090.68 1117.48 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
samsung asic 5-21 std130 spsram_hd high-density single-port synchronous static ram reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 8192 8192 12288 12288 16384 16384 32768 bpw 12 12 14 14 16 16 16 ba 1212122 timing (ns) t cyc 2.31 2.26 2.50 2.35 2.53 2.44 2.69 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.69 0.68 0.69 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.38 0.38 0.38 0.38 0.38 0.38 0.38 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.96 1.91 2.16 2.00 2.19 2.09 2.34 t da 1.44 1.32 1.63 1.40 1.65 1.48 1.70 t dz 0.11 0.11 0.11 0.11 0.12 0.12 0.12 t zd 0.14 0.14 0.15 0.15 0.15 0.15 0.15 t od 0.61 0.61 0.62 0.62 0.64 0.64 0.64 power ( w/mhz) power_read 178.79 194.59 222.44 226.86 251.10 260.48 296.20 power_write 189.75 204.73 236.25 241.90 274.10 281.34 321.90 power_standby 37.12 50.47 41.89 57.37 46.58 64.30 67.98 area ( m) width 1282.68 1314.84 1474.68 1512.20 1666.68 1709.56 1709.56 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
std130 5-22 samsung asic spsram_hd high-density single-port synchronous static ram timing diagrams read cycle write cycle t as a[] t ah (csn = low, oen = low, di = don? care) t acc wen t ws t wh t da dout[] t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a[] t ah (csn= low, oen = don? care) wen t ws t wh di[] t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
samsung asic 5-23 std130 spsram_hd high-density single-port synchronous static ram read cycle with csn controlled oen controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. t as a[] t ah (oen = low, wen = high, di = don? care) csn t cs t ch dout[] t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (ck, a, wen, di, csn = don? care) t od t dz hi-z valid oen dout[] hi-z t zd
std130 5-24 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write logic symbol function description spsrambw_hd is a single-port synchronous static ram with bit-write capability which is provided as a compiler. spsrambw_hd is intended for use in high-density applications. basically, its functionality is exactly same as spsram_hd except a bit-write operation which is controlled by bwen[], named bit-write enable signal bus. each bit of bwen[] enables or disables the write operation of its corresponding bit in di[]. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data bits in di[], which their corresponding bit(s) in bwen[] are low, are written into the memory location speci?d on a[]. when all bits of bwen[] are high, any data in di[] are not written into the memory location speci?d on a[]. when all bits of bwen[] are low, the data in di[] are written into the memory location speci?d on a[], which is exactly same as the write operation in spsram_hd. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. spsrambw_hd function table ck csn wen oen a bwen di dout comment x x x h x x x z unconditional tri-state output x h x l x x x dout(t-1) de-selected (standby mode) l l l valid all l valid dout(t-1) word-write cycle l l l valid l valid dout(t-1) bit-write cycle l l l valid all h valid dout(t-1) no operation l h l valid x x mem(a) read cycle features suitable for high-density application bit-write capability separated data i/o synchronous operation duty-free clock cycle asynchronous tristate output latched inputs and outputs automatic power-down zero standby current zero hold time low noise output optimization flexible aspect ratio dual-bank scheme available up to 512k bits capacity up to 32k number of words up to128 number of bit per word ck csn wen bwen [b-1:0] oen spsrambw_hd_xmb dout [b-1:0] a [m-1:0] notes: 1. words(w) is the number of words. 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. 4. banks(ba) is the number of banks. di [b-1:0] 5. m = ? log 2 w ?
samsung asic 5-25 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write parameter description spsrambw_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba) pin descriptions parameters ymux(y) = 4 ymux(y) = 8 ymux(y) = 16 ymux =(y) 32 words (w) ba = 1 min 32 64 128 256 max 2048 4096 8192 16384 step 16 32 64 128 ba = 2 min 64 128 256 512 max 4096 8192 16384 32768 step 32 64 128 256 bpw (b) min 2 2 2 2 max 128 64 32 16 step 1 1 1 1 name type description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writ- ing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. bwen[] bit-write enable bit-write enable input bus. the bit-write enable is latched into the ram on the rising edge of ck. each bit of bwen[] enables/disables the write operation of corresponding data bit. bwen[i] corresponds to di[i] in bit-write. if wen and bwen[0] are low and bwen[1] is high, di[0] is written into the memory location speci?d on a[], but di[1] is not written. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any input. when oen is high, dout is disabled and goes to high-impedance state. a[] address address input bus. the address is latched into the ram on the rising edge of ck. di[] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. dout[] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode.
std130 5-26 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write pin capacitance unit: [sl] note: each pin? capacitance is exactly same regardless of available mux types for same bank. block diagrams spsrambw_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from spsrambw_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the middle-edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. ck csn wen bwen oen a di dout 10.83 6.39 4.45 4.45 4.45 4.45 4.45 16.06 <1-bank architecture> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vdd vss vdd vss vdd vss vdd vss dout[b/2-1:0] di[b/2-1:0] a[m-1:0] wen oen csn ck dout[b-1:b/2] di[b-1:b/2] bwen[b-1:b/2] bwen[b/2-1:0]
samsung asic 5-27 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in spsrambw_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsrambw_hd. 4. a byte-write or word-write operation with spsrambw_hd. refer to the function table. in byte-write operation, the number of bwen[] signal bus should be divided by a byte (8) and eight bwen signals should be tied to a connection wire. in this case, di[] bus is controlled by a byte-wired bwen signal instead of each bwen bit. in word-write operation, the functionality is exactly same as spsram_hd. if all of bwen[] signal is tied to low state, di[] bus is only controlled by wen. 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver vss vdd vdd vss vdd vss vss vdd vdd vss vdd vss dout[b/2-1:0] di[b/2-1:0] a[m-1:0] wen oen csn ck dout[b-1:b/2] di[b-1:b/2] bwen[b-1:b/2] bwen[b/2-1:0]
std130 5-28 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckh clock pulse width high t ckl clock pulse width low t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t bws bwen setup time t bwh bwen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations. de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-29 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=4 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 128 256 256 512 512 768 768 bpw 32 32 48 48 64 64 80 80 ba 12121212 timing (ns) t cyc 1.92 1.92 1.98 1.96 2.08 2.03 2.18 2.10 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.69 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.38 0.39 0.37 0.37 0.37 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.54 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.37 0.38 0.36 0.37 0.35 0.36 0.34 0.36 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.56 1.56 1.61 1.60 1.70 1.66 1.79 1.72 t da 1.15 1.14 1.20 1.17 1.29 1.22 1.37 1.28 t dz 0.10 0.10 0.11 0.11 0.12 0.12 0.13 0.13 t zd 0.13 0.13 0.14 0.14 0.16 0.16 0.17 0.17 t od 0.58 0.58 0.60 0.60 0.62 0.62 0.65 0.65 power ( w/mhz) power_read 157.48 163.31 219.68 227.61 284.46 325.52 353.63 366.12 power_write 172.17 174.63 246.45 246.30 334.14 294.53 433.27 413.05 power_standby 53.81 57.95 73.45 79.33 93.10 101.37 113.19 124.29 area ( m) width 494.08 579.84 686.08 814.72 878.08 1049.60 1090.68 1305.08 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
std130 5-30 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=4 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.26 2.16 2.48 2.27 2.51 2.37 2.64 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.69 0.69 0.68 0.70 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.36 0.36 0.35 0.35 0.35 0.35 0.35 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.33 0.36 0.33 0.36 0.32 0.36 0.38 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.87 1.78 2.07 1.87 2.10 1.96 2.21 t da 1.44 1.32 1.63 1.40 1.65 1.47 1.70 t dz 0.13 0.13 0.14 0.14 0.14 0.14 0.14 t zd 0.18 0.18 0.18 0.18 0.19 0.19 0.19 t od 0.67 0.67 0.70 0.70 0.72 0.72 0.72 power ( w/mhz) power_read 421.51 436.46 501.16 515.06 569.39 597.00 649.35 power_write 538.10 502.70 683.61 614.11 835.34 735.04 876.66 power_standby 133.36 147.70 153.78 173.19 174.26 199.55 214.28 area ( m) width 1282.68 1539.96 1474.68 1774.84 1666.68 2009.72 2009.72 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
samsung asic 5-31 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 256 512 512 1024 1024 1536 1536 bpw 16 16 24 24 32 32 40 40 ba 12121212 timing (ns) t cyc 1.92 1.92 1.98 1.97 2.08 2.03 2.18 2.10 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.39 0.39 0.38 0.38 0.38 0.38 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.54 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.38 0.38 0.37 0.38 0.36 0.37 0.35 0.37 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.56 1.56 1.61 1.60 1.71 1.66 1.79 1.72 t da 1.16 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.10 0.10 0.11 0.11 0.11 0.11 t zd 0.12 0.12 0.13 0.13 0.14 0.14 0.15 0.15 t od 0.57 0.57 0.59 0.59 0.60 0.60 0.62 0.62 power ( w/mhz) power_read 127.53 131.30 174.82 179.30 224.78 229.48 278.95 283.56 power_write 143.81 147.19 201.38 203.63 267.29 264.71 340.57 331.31 power_standby 33.97 37.90 43.68 49.03 53.34 60.51 63.28 72.38 area ( m) width 494.08 536.96 686.08 750.40 878.08 963.84 1090.68 1197.88 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
std130 5-32 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.26 2.17 2.48 2.27 2.51 2.37 2.64 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.68 0.68 0.70 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.37 0.37 0.37 0.37 0.36 0.36 0.36 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.35 0.37 0.34 0.37 0.34 0.37 0.40 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.87 1.78 2.07 1.87 2.10 1.96 2.21 t da 1.44 1.32 1.63 1.40 1.65 1.47 1.70 t dz 0.12 0.12 0.12 0.12 0.13 0.13 0.13 t zd 0.16 0.16 0.16 0.16 0.17 0.17 0.17 t od 0.64 0.64 0.66 0.66 0.67 0.67 0.67 power ( w/mhz) power_read 331.78 336.04 396.20 394.46 449.45 455.18 494.97 power_write 416.35 398.54 517.95 478.72 617.05 564.19 647.66 power_standby 73.21 84.43 83.33 97.64 93.58 111.30 119.57 area ( m) width 1282.68 1411.32 1474.68 1624.76 1666.68 1838.20 1838.20 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
samsung asic 5-33 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 512 1024 1024 2048 2048 3072 3072 bpw 8 8 12 12 16 16 20 20 ba 12121212 timing (ns) t cyc 1.94 1.96 2.00 2.00 2.10 2.06 2.20 2.14 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.66 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.40 0.40 0.40 0.40 0.39 0.39 0.39 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.54 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.38 0.38 0.38 0.39 0.37 0.39 0.37 0.39 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.57 1.57 1.63 1.62 1.72 1.68 1.81 1.75 t da 1.16 1.16 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.10 0.10 0.10 0.10 0.11 0.11 t zd 0.12 0.12 0.13 0.13 0.13 0.13 0.14 0.14 t od 0.57 0.57 0.58 0.58 0.59 0.59 0.61 0.61 power ( w/mhz) power_read 98.20 101.88 130.75 134.91 165.98 169.75 205.12 208.08 power_write 107.31 111.32 144.95 148.68 188.25 189.21 237.29 234.18 power_standby 25.31 29.61 30.49 36.16 35.63 42.90 40.92 49.78 area ( m) width 494.08 515.52 686.08 718.24 878.08 920.96 1090.68 1144.28 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
std130 5-34 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.28 2.20 2.50 2.50 2.53 2.40 2.68 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.69 0.68 0.70 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.38 0.38 0.38 0.38 0.37 0.37 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.36 0.39 0.36 0.39 0.35 0.39 0.41 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.89 1.80 2.08 1.90 2.11 1.99 2.24 t da 1.44 1.32 1.63 1.40 1.65 1.47 1.70 t dz 0.11 0.11 0.12 0.12 0.12 0.12 0.12 t zd 0.15 0.15 0.15 0.15 0.16 0.16 0.16 t od 0.62 0.62 0.63 0.63 0.65 0.65 0.65 power ( w/mhz) power_read 242.79 244.56 293.00 286.30 331.49 330.11 363.08 power_write 286.67 278.46 355.19 331.39 416.48 387.85 441.04 power_standby 46.23 56.77 51.74 64.39 57.27 72.22 76.97 area ( m) width 1282.68 1347.00 1474.68 1549.72 1666.68 1752.44 1752.44 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
samsung asic 5-35 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 2048 2048 4096 4096 6144 6144 bpw 4466881010 ba 12121212 timing (ns) t cyc 1.97 2.02 2.03 2.06 2.13 2.13 2.23 2.20 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.66 0.68 0.66 0.68 0.67 0.68 0.68 0.68 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.41 0.41 0.40 0.40 0.39 0.39 0.39 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.54 0.54 0.54 0.54 0.54 0.54 0.53 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.40 0.42 0.39 0.42 0.38 0.41 0.38 0.41 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.60 1.64 1.65 1.68 1.74 1.73 1.83 1.80 t da 1.16 1.14 1.21 1.17 1.29 1.23 1.37 1.28 t dz 0.09 0.09 0.09 0.09 0.10 0.10 0.10 0.10 t zd 0.11 0.11 0.12 0.12 0.13 0.13 0.14 0.14 t od 0.56 0.56 0.57 0.57 0.59 0.59 0.60 0.60 power ( w/mhz) power_read 83.75 87.31 108.82 112.80 136.62 139.92 168.27 185.42 power_write 89.01 93.83 116.50 121.33 148.32 151.24 184.76 170.84 power_standby 20.91 25.81 23.58 29.81 26.22 33.90 28.96 38.06 area ( m) width 494.08 504.80 686.08 702.16 878.08 899.52 1090.68 1117.48 height 178.42 259.68 225.58 306.84 319.90 401.16 414.22 495.48
std130 5-36 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 8192 8192 12288 12288 16384 16384 32768 bpw 12 12 14 14 16 16 16 ba 1212122 timing (ns) t cyc 2.32 2.26 2.53 2.36 2.56 2.46 2.74 t ckl 0.61 0.61 0.61 0.61 0.61 0.61 0.61 t ckh 0.32 0.32 0.32 0.32 0.32 0.32 0.32 t as 0.68 0.68 0.69 0.68 0.70 0.68 0.67 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.31 0.31 0.31 0.31 0.31 0.31 0.31 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.38 0.38 0.38 0.38 0.38 0.38 0.38 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.54 0.53 0.54 0.53 0.54 0.53 0.51 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.38 0.41 0.37 0.41 0.37 0.41 0.43 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.91 1.86 2.11 1.95 2.14 2.04 2.29 t da 1.44 1.32 1.63 1.40 1.65 1.47 1.70 t dz 0.11 0.11 0.11 0.11 0.12 0.12 0.12 t zd 0.14 0.14 0.15 0.15 0.15 0.15 0.15 t od 0.61 0.61 0.62 0.62 0.64 0.64 0.64 power ( w/mhz) power_read 198.48 199.52 241.02 232.80 272.30 267.82 297.00 power_write 220.68 218.03 272.11 256.85 314.51 298.11 336.59 power_standby 31.71 42.26 34.69 46.84 37.72 51.52 54.50 area ( m) width 1282.68 1314.84 1474.68 1512.20 1666.68 1709.56 1709.56 height 508.54 589.80 697.18 778.44 885.82 967.08 1721.64
samsung asic 5-37 std130 spsrambw_hd high-density single-port synchronous static ram with bit-write timing diagrams read cycle write cycle t as a[] t ah (csn = low, oen = low, bwen, di = don? care) t acc wen t ws t wh t da dout[] t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a[] t ah (csn= low, oen = don? care) wen t ws t wh di[] t cyc ck t ckl t ckh a0 a2 bw1 t ds t dh d0 d2 d1 t bws bwen[] t bwh bw0 bw2 a1
std130 5-38 samsung asic spsrambw_hd high-density single-port synchronous static ram with bit-write read cycle with csn-controlled oen-controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. t as a[] t ah (oen = low, wen = high, bwen, di = don? care) csn t cs t ch dout[] t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (csn, ck, a, wen, bwen, di = don? care) t od t dz hi-z valid oen dout[] hi-z t zd
samsung asic 5-39 std130 spsramr_hd single-port synchronous static ram with redundancy logic symbol function description spsramr_hd is a repairable single-port synchronous static ram with bit-write capability which is provided as a compiler. spsramr_hd is intended for use in high-capacity applications. basically, its functionality is exactly same as spsrambw_hd. each bit of bwen[] enables or disable the write operation of its corresponding bit in di[]. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low. the data bytes or bits in di[], which their corresponding bit(s) in bwen[] are low, are written into the memory location speci?d on a[]. when all bits of bwen[] are high, any data in di[] are not written into the memory location speci?d on a[]. when all bits of bwen[] are low, the data in di[] are written into the memory location speci?d on a[], which is exactly same as the write operation in spsram_hd. during the write cycle, dout[] remains stable. on the rising edge of ck, the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. spsramr_hd function table ck csn wen oen a bwen di dout comment x x x h x x x z unconditional tri-state output x h x l x x x dout(t-1) de-selected (standby mode) l l l valid all l valid dout(t-1) word-write cycle l l l valid l/h valid dout(t-1) bit-write cycle l l l valid all h valid dout(t-1) no operation l h l valid x x mem(a) read cycle features suitable for high-capacity application heuristic row-redundancy available bit-write capability separated data i/o synchronous operation duty-free clock cycle asynchronous tri-state output control latched inputs and outputs automatic power-down zero standby current zero hold time low noise output optimization flexible aspect ratio dual-bank scheme available 64kbits ~ 1mbits capacity 2k ~ 32k number of words 8 ~ 128 number of bits per word notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bit per word. 3. ymux (y) is one of the column mux types. 5. m = ? log 2 w ? ck csn wen spsramr_hd_xmb dout [b-1:0] oen a [m-1:0] di [b-1:0] 4. banks(ba) is the number of banks. bwen[b-1:0]
std130 5-40 samsung asic spsramr_hd single-port synchronous static ram with redundancy parameter description spsramr_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). pin descriptions parameters ymux(y) = 8 ymux(y) = 16 ymux(y) = 32 words (w) ba = 1 min 2048 4096 8192 max 4096 8192 16384 step 64 128 256 ba = 2 min 4096 8192 16384 max 8192 16384 32768 step 128 256 512 bpw (b) min 32 16 8 max 128 64 32 step 1 1 1 name type description ck clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previ- ous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are present at dout. bwen[] bit-write enable bit-write enable input bus. the bit-write enable is latched into the ram on the rising edge of ck. each bit of bwen[] enables/disables the write operation of corresponding data bit. bwen[i] corresponds to di[i] in bit-write. if wen and bwen[0] are low and bwen[1] is high, di[0] is written into the memory loca- tion speci?d on a[], but di[1] is not written. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any input. when oen is high, dout is disabled and goes to high-impedance state. a[] address address input bus. the address is latched into the ram on the rising edge of ck. di[] data input data input bus. data are latched on the rising edge of ck. data input is writ- ten into the addressed location in write mode. dout[] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode.
samsung asic 5-41 std130 spsramr_hd single-port synchronous static ram with redundancy pin capacitance (unit = sl) note: each pin? capacitance is exactly same regardless of available mux types for same bank block diagrams spsramr_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from spsramr_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the middle-edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the top-edge, the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. ck csn wen bwen oen a di dout 12.0309 2.7273 2.8433 3.1528 4.7002 2.9594 3.0754 11.2573 <1-bank architecture> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vdd vss vdd vss vdd vss vdd vss dout[b-1:b/2] di[b-1:b/2] a[m-1:0] wen oen csn ck dout[b/2-1:0] di[b/2-1:0] bwen[b-1:b/2] bwen[b/2-1:0]
std130 5-42 samsung asic spsramr_hd single-port synchronous static ram with redundancy application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in spsramr_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of spsramr_hd. 4. a byte-write or word-write operation with spsramr_hd. refer to the function table. in byte-write operation, the number of bwen[] signal bus should be divided by a byte (8) and eight bwen signals should be tied to a connection wire. in this case, di[] bus is controlled by a byte-wired bwen signal instead of each bwen bit. in word-write operation, the functionality is exactly same as spsram_hd. if all of bwen[] signal is tied to low state, di[] bus is only controlled by wen. 5. power reduction during standby mode. the standby power is measured on the condition that only csn is disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver vss vdd vdd vss vdd vss vss vdd vdd vss vdd vss dout[b-1:b/2] di[b-1:b/2] a[m-1:0] wen oen csn ck dout[b/2-1:0] di[b/2-1:0] bwen[b-1:b/2] bwen[b/2-1:0]
samsung asic 5-43 std130 spsramr_hd single-port synchronous static ram with redundancy characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckl clock pulse width low t ckh clock pulse width high t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t bws bwen setup time t bwh bwen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations. de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
std130 5-44 samsung asic spsramr_hd single-port synchronous static ram with redundancy reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode. parameters words 2048 4096 2048 4096 4096 8192 4096 8192 bpw 32 32 64 64 64 64 128 128 ba 12121212 timing (ns) t cyc 2.80 2.86 2.84 2.91 3.04 3.06 3.19 3.24 t ckl 0.46 0.46 0.46 0.46 0.46 0.46 0.46 0.46 t ckh 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 t as 0.41 0.43 0.41 0.43 0.41 0.44 0.41 0.44 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.48 0.48 0.47 0.47 0.47 0.47 0.47 0.47 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.52 0.52 0.51 0.51 0.51 0.51 0.50 0.50 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.66 2.73 2.70 2.77 2.71 2.83 2.83 2.95 t da 2.39 2.41 2.40 2.43 2.40 2.46 2.41 2.47 t dz 0.24 0.24 0.25 0.25 0.25 0.25 0.26 0.26 t zd 0.38 0.38 0.40 0.40 0.40 0.40 0.40 0.40 t od 0.61 0.60 0.67 0.66 0.67 0.66 0.82 0.81 power ( w/mhz) power_read 277.12 386.29 483.65 675.99 491.41 702.04 914.21 1312.40 power_write 334.47 452.57 597.93 807.05 667.45 890.56 1282.10 1704.30 power_standby 61.78 80.26 108.30 138.09 109.03 147.26 203.89 273.41 area ( m) width 998.96 1084.72 1766.96 1938.48 1766.96 1938.48 3302.96 3646.00 height 521.58 991.64 521.58 991.64 912.54 1773.56 926.22 1800.92
samsung asic 5-45 std130 spsramr_hd single-port synchronous static ram with redundancy reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode. parameters words 4096 8192 4096 8192 8192 16384 8192 16384 bpw 16 16 32 32 32 32 64 64 ba 12121212 timing (ns) t cyc 2.81 2.89 2.86 2.94 3.03 3.06 3.24 3.23 t ckl 0.46 0.46 0.46 0.46 0.46 0.46 0.46 0.46 t ckh 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 t as 0.42 0.43 0.41 0.43 0.41 0.44 0.41 0.44 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.48 0.48 0.47 0.47 0.47 0.47 0.47 0.47 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.52 0.52 0.51 0.51 0.51 0.51 0.51 0.51 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.68 2.76 2.72 2.80 2.73 2.86 2.84 2.97 t da 2.39 2.41 2.40 2.43 2.40 2.46 2.41 2.47 t dz 0.24 0.24 0.25 0.25 0.25 0.25 0.26 0.26 t zd 0.38 0.38 0.40 0.39 0.39 0.39 0.40 0.40 t od 0.60 0.60 0.64 0.64 0.64 0.64 0.76 0.76 power ( w/mhz) power_read 260.05 376.36 450.22 655.49 456.53 675.58 846.09 1261.50 power_write 288.84 414.41 506.58 732.14 545.08 779.81 1028.90 1475.50 power_standby 49.71 74.36 84.16 126.45 84.94 132.21 155.73 243.85 area ( m) width 998.96 1041.84 1766.96 1852.72 1766.96 1852.72 3302.96 3474.48 height 521.58 991.64 521.58 991.64 912.54 1773.56 926.22 1800.92
std130 5-46 samsung asic spsramr_hd single-port synchronous static ram with redundancy reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on condition that other signals are in normal operation while csn is in disable mode. parameters words 8192 16384 8192 16384 16384 32768 16384 32768 bpw 8 8 16 16 16 16 32 32 ba 12121212 timing (ns) t cyc 2.84 2.95 2.89 3.00 3.38 3.41 3.23 3.22 t ckl 0.46 0.46 0.46 0.46 0.46 0.46 0.46 0.46 t ckh 0.27 0.27 0.27 0.27 0.27 0.27 0.27 0.27 t as 0.41 0.43 0.41 0.43 0.41 0.44 0.41 0.44 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.29 0.29 0.29 0.29 0.29 0.29 0.29 0.29 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.48 0.48 0.48 0.48 0.48 0.48 0.47 0.47 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.44 0.44 0.44 0.44 0.44 0.44 0.44 0.44 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.52 0.52 0.51 0.51 0.51 0.61 0.51 0.51 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.71 2.81 2.75 2.85 2.79 2.94 2.87 3.03 t da 2.39 2.41 2.40 2.43 2.41 2.47 2.41 2.47 t dz 0.23 0.23 0.25 0.25 0.25 0.24 0.25 0.25 t zd 0.38 0.38 0.39 0.39 0.39 0.39 0.39 0.39 t od 0.59 0.59 0.63 0.63 0.63 0.63 0.74 0.74 power ( w/mhz) power_read 246.92 362.59 423.44 625.55 429.95 644.95 792.78 1198.40 power_write 261.59 385.51 451.63 674.63 474.24 706.05 881.78 1322.70 power_standby 39.67 63.33 63.98 104.32 64.81 108.28 115.27 195.47 area ( m) width 998.96 1020.40 1766.96 1809.84 1766.96 1809.84 3302.96 3388.72 height 521.58 991.64 521.58 991.64 912.54 1773.56 926.22 1800.92
samsung asic 5-47 std130 spsramr_hd single-port synchronous static ram with redundancy timing diagrams read cycle write cycle t as a[] t ah (csn = low, oen = low, bwen, di = don? care) t acc wen t ws t wh t da dout[] t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a[] t ah (csn= low, oen = don? care) wen t ws t wh di[] t cyc ck t ckl t ckh a0 a2 bw1 t ds t dh d0 d2 d1 t bws bwen[] t bwh bw0 bw2 a1
std130 5-48 samsung asic spsramr_hd single-port synchronous static ram with redundancy read cycle with csn-controlled oen-controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. t as a[] t ah (oen = low, wen = high, bwen, di = don? care) csn t cs t ch dout[] t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (csn, ck, a, wen, bwen, di = don? care) t od t dz hi-z valid oen dout[] hi-z t zd
samsung asic 5-49 std130 dpsram_hd high-density dual-port synchronous static ram logic symbol function description dpsram_hd is a dual-port synchronous static ram which is provided as a compiler. dpsram_hd is intended for use in high-density applications. each port is fully independent. on the rising edge of ck1(ck2), the write cycle is initiated when wen1 (wen2) is low and csn1 (csn2) is low. the data on di1[] (di2[]) is written into the memory location speci?d on a1[](a2[]). during the write cycle, dout1[] (dout2[]) remains stable. on the rising edge of ck, the read cycle is initiated when wen1 (wen2) is high and csn1(csn2) is low. the data at dout1[] (dout2[]) become valid after a delay. while in standby mode that csn1(csn2) is high, a1[](a2[]) and di1[] (di2[]) are disabled, data stored in the memory is retained and dout1[] (dout2[]) remains stable. when oen1 (oen2) is high, dout1[] (dout2[]) is placed in a high-impedance state. dpsram_hd function table ck1 ck2 csn1 csn2 wen1 wen2 oen1 oen2 a1 a2 di1 di2 dout1 dout2 comment x x x h x x z unconditional tri-state output x h x l x x dout(t-1) de-selected (standby mode) l l l valid valid dout(t-1) write cycle l h l valid x mem(a) read cycle features suitable for high-density application separated data i/o synchronous operation duty-free clock cycle asynchronous tri-state output control latched inputs and outputs automatic power-down zero standby current zero hold time low noise output optimization flexible aspect ratio up to 256k bits capacity up to 16k number of words up to 128 number of bits per word notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 4. m = ? log 2 w ? ck1 ck2 csn1 csn2 wen1 dpsram_hd_xm dout1 [b-1:0] wen2 oen1 oen2 a1 [m-1:0] a2 [m-1:0] di1 [b-1:0] di2 [b-1:0] dout2 [b-1:0]
std130 5-50 samsung asic dpsram_hd high-density dual-port synchronous static ram parameter description dpsram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y). pin descriptions pin capacitance (unit = sl) note: each pin? capacitance is exactly same regardless of available mux types. parameters ymux(y) = 4 ymux(y) = 8 ymux(y) = 16 ymux(y) = 32 words (w) min 32 64 128 256 max 2048 4096 8192 16384 step 16 32 64 128 bpw (b) min 1111 max 128 64 32 16 step 1111 name type description ck1 ck2 clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. csn1 csn2 chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previ- ous data output. wen1 wen2 read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. oen1 oen2 data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a1 [ ] a2 [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di1 [ ] di2 [ ] data input data input bus. data are latched on the rising edge of ck. data input is writ- ten into the addressed location in write mode. dout1 [ ] dout2 [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a di dout 31.43 4.55 4.55 10.97 4.55 5.16 33.58
samsung asic 5-51 std130 dpsram_hd high-density dual-port synchronous static ram block diagram dpsram_hd supports only 1-bank architecture. the power ports are located on the top edge and the bottom edge of both right- and left-sides of the memory. however, dpsram_hd has two symmetrical ports located on opposite edges of memory. port1 is located on the bottom of the memory while port2 is located on the top of the memory. i/o driver address & clock buffers i/o driver y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vdd vss dout1[b/2-1:0] di1[b/2-1:0] a1[m-1:0] wen1 csn1 ck1 oen1 di1[b-1:b/2] dout1[b-1:b/2] vss vdd vdd vss vss vdd dout2[b/2-1:0] di2[b/2-1:0] a2[m-1:0] wen2 csn2 ck2 oen2 di2[b-1:b/2] dout2[b-1:b/2]
std130 5-52 samsung asic dpsram_hd high-density dual-port synchronous static ram application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in dpsram_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of dpsram_hd. 4. contention mode in same address access in dpsram_hd, simultaneous operation by both ports on the same memory address, as write/write, write/read or read/write operation, causes a contention problem. simultaneous operation is de?ed as a state in which both ports are enabled, both address buses are equal at the rising edge of ck. dpsram_hd has no scheme preventing the contention. due to simultaneous operation, silicon will behave unpredictably. a write operation cannot end and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. in write/write operation, the data stored at the current address will be unpredictable. in write/read or read/write operation, the read port is invalid while the write port is still valid. if you want to avoid the contention mode, you have to give the value greater than tcc (clock-to-clock setup time). however, simultaneous read/read is allowable without any restrictions. 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode.
samsung asic 5-53 std130 dpsram_hd high-density dual-port synchronous static ram characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckl clock pulse width low t ckh clock pulse width high t cc clock-to-clock setup time t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
std130 5-54 samsung asic dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 64 128 256 512 768 1024 1536 2048 bpw 16 32 48 64 80 96 112 128 timing (ns) t cyc 1.79 1.84 1.91 2.03 2.15 2.28 2.44 2.52 t ckl 0.66 0.64 0.61 0.58 0.61 0.60 0.59 0.60 t ckh 0.27 0.27 0.27 0.27 0.28 0.28 0.28 0.28 t cc 0.71 0.76 0.84 0.97 1.06 1.20 1.44 1.54 t as 0.38 0.38 0.38 0.39 0.36 0.36 0.36 0.36 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.37 0.40 0.39 0.38 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.58 0.55 0.52 0.50 0.48 0.47 0.45 0.44 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.36 0.36 0.37 0.38 0.34 0.33 0.35 0.35 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.56 1.61 1.68 1.80 1.93 2.05 2.22 2.29 t da 1.55 1.58 1.63 1.76 1.86 1.96 2.15 2.17 t dz 0.42 0.45 0.48 0.51 0.52 0.55 0.58 0.60 t zd 0.45 0.51 0.56 0.61 0.62 0.65 0.68 0.70 t od 0.52 0.58 0.64 0.71 0.72 0.75 0.77 0.80 power ( w/mhz) power_read 86.57 145.15 206.80 275.22 352.35 428.99 522.52 602.97 power_write 93.87 162.77 238.31 329.22 433.18 541.78 692.24 844.24 power_standby 32.22 50.80 70.69 93.20 117.23 140.72 169.47 198.71 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
samsung asic 5-55 std130 dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 256 512 1024 1536 2048 3072 4096 bpw 8 16243240485664 timing (ns) t cyc 1.81 1.85 1.92 2.05 2.17 2.29 2.48 2.54 t ckl 0.69 0.66 0.63 0.61 0.61 0.59 0.60 0.56 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.27 t cc 0.72 0.77 0.85 0.97 1.07 1.20 1.45 1.52 t as 0.40 0.39 0.38 0.38 0.38 0.38 0.36 0.36 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.57 0.54 0.52 0.49 0.49 0.47 0.46 0.45 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.35 0.35 0.35 0.36 0.36 0.36 0.37 0.37 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.58 1.62 1.69 1.82 1.94 2.06 2.26 2.31 t da 1.56 1.59 1.64 1.78 1.87 1.97 2.17 2.18 t dz 0.42 0.45 0.48 0.50 0.52 0.55 0.57 0.60 t zd 0.45 0.50 0.55 0.60 0.62 0.65 0.67 0.70 t od 0.52 0.58 0.64 0.70 0.72 0.75 0.77 0.79 power ( w/mhz) power_read 79.56 131.01 185.55 246.88 317.25 384.80 469.11 540.44 power_write 80.16 134.69 194.05 264.44 345.51 427.28 538.42 644.00 power_standby 27.67 41.76 57.15 75.12 94.56 113.48 137.79 162.28 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
std130 5-56 samsung asic dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 512 1024 2048 3072 4096 6144 8192 bpw 4 8 12 16 20 24 28 32 timing (ns) t cyc 1.81 1.87 1.96 2.10 2.19 2.32 2.51 2.58 t ckl 0.68 0.66 0.63 0.61 0.61 0.61 0.60 0.60 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.28 t cc 0.70 0.76 0.84 0.97 1.07 1.19 1.46 1.56 t as 0.37 0.37 0.37 0.38 0.37 0.36 0.36 0.33 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.56 0.54 0.52 0.49 0.49 0.49 0.48 0.47 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.35 0.33 0.33 0.36 0.33 0.33 0.34 0.35 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.61 1.65 1.73 1.87 1.98 2.09 2.31 2.35 t da 1.58 1.62 1.69 1.81 1.90 1.99 2.19 2.19 t dz 0.42 0.45 0.47 0.50 0.52 0.54 0.57 0.59 t zd 0.43 0.49 0.54 0.60 0.62 0.64 0.67 0.69 t od 0.51 0.57 0.64 0.70 0.72 0.74 0.77 0.79 power ( w/mhz) power_read 76.17 123.87 174.58 231.92 298.86 362.11 442.21 509.19 power_write 73.15 119.65 170.12 229.53 298.73 366.36 457.35 538.52 power_standby 24.96 36.26 48.85 64.01 80.75 96.46 117.52 138.75 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
samsung asic 5-57 std130 dpsram_hd high-density dual-port synchronous static ram reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsram_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 1024 2048 4096 6144 8192 12288 16384 bpw 2 4 6 8 10 12 14 16 timing (ns) t cyc 1.87 1.93 2.01 2.12 2.24 2.35 2.55 2.62 t ckl 0.68 0.66 0.65 0.64 0.64 0.64 0.63 0.63 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.28 t cc 0.69 0.75 0.84 0.98 1.06 1.20 1.46 1.53 t as 0.37 0.37 0.37 0.38 0.37 0.36 0.34 0.34 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.56 0.54 0.53 0.52 0.52 0.52 0.51 0.51 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.28 0.30 0.33 0.36 0.36 0.37 0.37 0.38 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.63 1.68 1.76 1.89 2.02 2.13 2.33 2.38 t da 1.62 1.64 1.70 1.85 1.96 2.05 2.24 2.25 t dz 0.43 0.45 0.48 0.50 0.52 0.54 0.57 0.59 t zd 0.53 0.54 0.56 0.60 0.62 0.64 0.67 0.69 t od 0.63 0.64 0.65 0.70 0.72 0.74 0.77 0.79 power ( w/mhz) power_read 74.46 120.29 169.15 224.65 290.25 351.11 428.95 493.53 power_write 70.27 112.47 158.24 212.03 275.64 335.98 416.64 485.50 power_standby 26.63 33.47 44.60 58.31 73.82 87.94 107.34 127.04 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
std130 5-58 samsung asic dpsram_hd high-density dual-port synchronous static ram timing diagrams read cycle write cycle t as a[] t ah (csn = low, oen = low, di[] = don? care) t acc wen t ws t wh t da dout[] t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a[] t ah (csn= low, oen = don? care) wen t ws t wh di[] t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1
samsung asic 5-59 std130 dpsram_hd high-density dual-port synchronous static ram read cycle with csn-controlled oen-controlled output enable contention mode note: ?on't care?means the condition that these pins are in normal operation mode. t as a[] t ah (oen = low, wen = high, di[] = don? care) csn t cs t ch dout[] t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (csn, ck, a[], wen, di[] = don? care) t od t dz hi-z valid oen dout[] hi-z t zd ck1 tcc ck2 (a1[] = a2[])
std130 5-60 samsung asic dpsrambw_hd high-density dual-port synchronous static ram with bit-write logic symbol function description dpsrambw_hd is a dual-port synchronous static ram with bit-write capability which is provided as a compiler. dpsrambw_hd is intended for use in high-density applications. each port is fully independent. basically, its functionality is exactly same as dpsram_hd except a bit-write operation which is controlled by bwen1[](bwen2[]), named bit-write enable signal bus. each bit of bwen1[](bwen2[]) enables or disable the write operation of its corresponding bit in di1[](di2[]). on the rising edge of ck1(ck2), the write cycle is initiated when wen1(wen2) is low and csn1(csn2) is low. the data bits in di1[](di2[]), which their corresponding bit(s) in bwen1[](bwen2[]) are low, are written into the memory location speci?d on a1[](a2[]). when all bits of bwen1[](bwen2[]) are high, any data in di1[](di2[]) are not written into the memory location speci?d on a1[](a2[]). when all bits of bwen1[](bwem2[]) are low, the data in di1[](di2[]) are written into the memory location speci?d on a1[](a2[]), which is exactly same as the write operation in dpsrambw_hd. during the write cycle, dout1[](dout2[]) remains stable. on the rising edge of ck1(ck2), the read cycle is initiated when wen1(wen2) is high and csn1(csn2) is low. the data at dout1[](dout2[]) become valid after a delay. while in standby mode that csn1(csn2) is high, a1[](a2[]) and di1[](di2[]) are disabled, data stored in the memory is retained and dout1[](dout2[]) remains stable. when oen1(oen2) is high, dout1[](dout2[]) is placed in a high-impedance state. dpsrambw_hd function table ck1 ck2 csn1 csn2 wen1 wen2 oen1 oen2 a1 a2 bwen1 bwen2 di1 di2 dout1 dout2 comment x x x h x x x z unconditional tri-state output x h x l x x x dout(t-1) de-selected (standby mode) l l l valid all l valid dout(t-1) word-write cycle l l l valid l valid dout(t-1) bit-write cycle l l l valid all h valid dout(t-1) no operation l h l valid x x mem(a) read cycle features suitable for high-density application separated data i/o synchronous operation duty-free clock cycle asynchronous tri-state output control latched inputs and outputs automatic power-down zero standby current zero hold time low noise output optimization flexible aspect ratio up to 256k bits capacity up to 16k number of words up to 128 number of bits per word 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 4. m = ? log 2 w ? ck1 ck2 csn1 csn2 wen1 dpsrambw_hd_xm dout1 [b-1:0] wen2 oen1 oen2 a1 [m-1:0] a2 [m-1:0] di1 [b-1:0] di2 [b-1:0] dout2 [b-1:0] notes: 1. words (w) is the number of words. bwen1[b-1:0] bwen2[b-1:0]
samsung asic 5-61 std130 dpsrambw_hd high-density dual-port synchronous static ram with bit-write parameter description dpsrambw_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y). pin descriptions pin capacitance (unit = sl) note: each pin? capacitance is exactly same regardless of available mux types. parameters ymux(y) = 4 ymux(y) = 8 ymux(y) = 16 ymux(y) = 32 words (w) min 32 64 128 256 max 2048 4096 8192 16384 step 16 32 64 128 bpw (b) min 1111 max 128 64 32 16 step 1111 name type description ck1 ck2 clock clock input. csn, wen, a[] and di[] are latched into the ram on the rising edge of ck. if csn and wen are low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in read mode. upon the falling edge of ck, the ram is in a precharge state. csn1 csn2 chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low, the ram is enabled for reading or writing, depending on the state of wen. when csn is high, the ram goes to the standby mode and is disabled for reading or writing. dout remains previ- ous data output. wen1 wen2 read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck. when wen is low, data are written to the addressed location and dout remains stable. when wen is high, data from the addressed word are presented at dout. bwen1[ ] bwen2[ ] bit-write enable bit-write enable input bus. the bit-write enable is latched into the ram on the rising edge of ck. each bit of bwen[] enables/disables the write operation of corresponding data bit. bwen[i] corresponds to di[i] in bit-write. if wen and bwen[0] are low and bwen[1] is high, di[0] is written into the memory loca- tion speci?d on a[], but di[1] is not written. oen1 oen2 data output enable data output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. a1 [ ] a2 [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di1 [ ] di2 [ ] data input data input bus. data are latched on the rising edge of ck. data input is writ- ten into the addressed location in write mode. dout1 [ ] dout2 [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode. ck csn wen oen a bwen di dout 31.43 4.55 4.55 10.97 4.55 5.16 5.16 33.58
std130 5-62 samsung asic dpsrambw_hd high-density dual-port synchronous static ram bit-write block diagram dpsrambw_hd supports only 1-bank architecture. the power ports are located on the top edge and the bottom edge of both right- and left-sides of the memory. however, dpsrambw_hd has two symmetrical ports located on opposite edges of memory. port1 is located on the bottom of the memory while port2 is located on the top of the memory. i/o driver address & clock buffers i/o driver y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vdd vss dout1[b/2-1:0] di1[b/2-1:0] a1[m-1:0] wen1 csn1 ck1 oen1 di1[b-1:b/2] dout1[b-1:b/2] vss vdd vdd vss vss vdd dout2[b/2-1:0] di2[b/2-1:0] a2[m-1:0] wen2 csn2 ck2 oen2 di2[b-1:b/2] dout2[b-1:b/2] bwen2[b-1:b/2] bwen2[b/2-1:0] bwen1[b-1:b/2] bwen1[b/2-1:0]
samsung asic 5-63 std130 dpsrambw_hd high-density dual-port synchronous static ram with bit-write application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in dpsrambw_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of dpsrambw_hd. 4. contention mode in same address access in dpsrambw_hd, simultaneous operation by both ports on the same memory address, as write/write, write/read or read/write operation, causes a contention problem. simultaneous operation is de?ed as a state in which both ports are enabled, both address buses are equal at the rising edge of ck. dpsrambw_hd has no scheme preventing the contention. due to simultaneous operation, silicon will behave unpredictably. a write operation cannot end and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. in write/write operation, the data stored at the current address will be unpredictable. in write/read or read/write operation, the read port is invalid while the write port is still valid. if you want to avoid the contention mode, you have to give the value greater than tcc (clock-to-clock setup time). however, simultaneous read/read is allowable without any restrictions. 5. a byte-write or word-write operation with dpsrambw_hd refer to the function table. in byte-write operation, the number of bwen[] signal bus should be divided by a byte (8) and eight bwen signals should be tied to a connection wire. in this case, di[] bus is controlled by a byte-wired bwen signal instead of each bwen bit. in word-write operation, the functionality is exactly same as dpsram_hd. if all of bwen[] signal is tied to low state, di[] bus is only controlled by wen. 6. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode.
std130 5-64 samsung asic dpsrambw_hd high-density dual-port synchronous static ram with bit-write characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ckl clock pulse width low t ckh clock pulse width high t cc clock-to-clock setup time t as address setup time t ah address hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t ws wen setup time t wh wen hold time t bws bwen setup time t bwh bwen hold time t acc data access time t da de-access time t dz dout drive to high-z time t zd dout high-z to drive time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations. de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-65 std130 dpsrambw_hd high-density dual-port synchronous static ram with bit-write reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsrambw_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 64 128 256 512 768 1024 1536 2048 bpw 16 32 48 64 80 96 112 128 timing (ns) t cyc 1.79 1.84 1.91 2.03 2.15 2.28 2.44 2.52 t ckl 0.66 0.64 0.61 0.58 0.61 0.60 0.59 0.60 t ckh 0.27 0.27 0.27 0.27 0.28 0.28 0.28 0.28 t cc 0.71 0.76 0.84 0.97 1.06 1.20 1.44 1.54 t as 0.38 0.38 0.38 0.39 0.36 0.36 0.36 0.36 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.37 0.40 0.39 0.38 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.58 0.55 0.52 0.50 0.48 0.47 0.45 0.44 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.36 0.36 0.37 0.38 0.34 0.33 0.35 0.35 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.55 0.52 0.50 0.47 0.44 0.42 0.39 0.36 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.56 1.61 1.68 1.80 1.93 2.05 2.22 2.29 t da 1.55 1.58 1.63 1.76 1.86 1.96 2.15 2.17 t dz 0.42 0.45 0.48 0.51 0.52 0.55 0.58 0.60 t zd 0.45 0.51 0.56 0.61 0.62 0.65 0.68 0.70 t od 0.52 0.58 0.64 0.71 0.72 0.75 0.77 0.80 power ( w/mhz) power_read 91.12 154.23 220.42 293.39 375.06 456.18 554.19 639.15 power_write 98.41 171.85 251.94 347.39 455.89 568.97 723.90 880.42 power_standby 36.77 59.89 84.32 111.37 139.94 167.91 201.14 234.89 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
std130 5-66 samsung asic dpsrambw_hd high-density dual-port synchronous static ram with bit-write reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsrambw_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 256 512 1024 1536 2048 3072 4096 bpw 8 16243240485664 timing (ns) t cyc 1.81 1.85 1.92 2.05 2.17 2.29 2.48 2.54 t ckl 0.69 0.66 0.63 0.61 0.61 0.59 0.60 0.56 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.27 t cc 0.72 0.77 0.85 0.97 1.07 1.20 1.45 1.52 t as 0.40 0.39 0.38 0.38 0.38 0.38 0.36 0.36 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.57 0.54 0.52 0.49 0.49 0.47 0.46 0.45 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.35 0.35 0.35 0.36 0.36 0.37 0.37 0.37 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.54 0.52 0.49 0.46 0.45 0.42 0.40 0.37 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.58 1.62 1.69 1.82 1.94 2.06 2.26 2.31 t da 1.56 1.59 1.64 1.78 1.87 1.97 1.17 2.18 t dz 0.42 0.45 0.48 0.50 0.52 0.55 0.57 0.60 t zd 0.45 0.50 0.55 0.60 0.62 0.65 0.67 0.70 t od 0.52 0.58 0.64 0.70 0.72 0.75 0.77 0.79 power ( w/mhz) power_read 81.83 135.56 192.36 255.97 328.59 398.39 484.95 558.54 power_write 82.44 139.23 200.86 273.53 356.85 440.87 554.26 662.10 power_standby 29.94 46.31 63.97 84.21 105.90 127.07 153.63 180.38 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
samsung asic 5-67 std130 dpsrambw_hd high-density dual-port synchronous static ram with bit-write reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsrambw_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 512 1024 2048 3072 4096 6144 8192 bpw 4 8 12 16 20 24 28 32 timing (ns) t cyc 1.81 1.87 1.96 2.10 2.19 2.32 2.51 2.58 t ckl 0.68 0.66 0.63 0.61 0.61 0.61 0.60 0.60 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.28 t cc 0.70 0.76 0.84 0.97 1.07 1.19 1.46 1.56 t as 0.37 0.37 0.37 0.38 0.37 0.36 0.36 0.33 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.56 0.54 0.52 0.49 0.49 0.49 0.48 0.47 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.35 0.33 0.33 0.36 0.33 0.33 0.34 0.35 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.54 0.51 0.49 0.46 0.45 0.42 0.40 0.37 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.61 1.65 1.73 1.87 1.98 2.09 2.31 2.35 t da 1.58 1.62 1.69 1.81 1.90 1.99 2.19 2.19 t dz 0.42 0.45 0.47 0.50 0.52 0.54 0.57 0.59 t zd 0.43 0.49 0.54 0.60 0.62 0.64 0.67 0.69 t od 0.51 0.57 0.64 0.70 0.72 0.74 0.77 0.79 power ( w/mhz) power_read 77.31 126.14 177.99 236.46 304.40 368.91 450.15 518.24 power_write 74.29 121.92 173.52 234.07 304.40 373.15 465.28 547.56 power_standby 26.09 38.53 52.26 68.56 86.42 103.26 125.45 147.80 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
std130 5-68 samsung asic dpsrambw_hd high-density dual-port synchronous static ram with bit-write reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) notes: 1. in power consumption of dpsrambw_hd, only one port is measured and the other port is isolated. 2. standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 1024 2048 4096 6144 8192 12288 16384 bpw 2 4 6 8 10 12 14 16 timing (ns) t cyc 1.87 1.93 2.01 2.12 2.24 2.35 2.55 2.62 t ckl 0.68 0.66 0.65 0.64 0.64 0.64 0.63 0.63 t ckh 0.28 0.28 0.28 0.28 0.28 0.28 0.28 0.28 t cc 0.69 0.75 0.84 0.98 1.06 1.20 1.46 1.53 t as 0.37 0.37 0.37 0.38 0.37 0.36 0.34 0.34 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ds 0.56 0.54 0.53 0.52 0.52 0.52 0.51 0.51 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t ws 0.28 0.30 0.33 0.36 0.36 0.37 0.37 0.38 t wh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.55 0.52 0.49 0.46 0.44 0.42 0.40 0.37 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.63 1.68 1.76 1.89 2.02 2.13 2.33 2.38 t da 1.62 1.64 1.70 1.85 1.96 2.05 2.24 2.25 t dz 0.43 0.45 0.48 0.50 0.52 0.54 0.57 0.59 t zd 0.53 0.54 0.56 0.60 0.62 0.64 0.67 0.69 t od 0.63 0.64 0.65 0.70 0.72 0.74 0.77 0.79 power ( w/mhz) power_read 75.03 121.43 170.85 226.91 293.08 354.51 432.91 498.06 power_write 70.84 113.61 159.95 214.30 278.48 339.39 420.60 490.03 power_standby 24.20 34.61 46.31 60.58 76.65 91.34 111.30 131.56 area ( m) width 548.20 893.80 1239.40 1585.00 2008.60 2354.20 2699.80 3045.40 height 194.12 217.72 264.92 359.32 453.60 547.86 736.38 925.16
samsung asic 5-69 std130 dpsrambw_hd high-density dual-port synchronous static ram with bit-write timing diagrams read cycle write cycle t as a[] t ah (csn = low, oen = low, di[], bwen[]= don? care) t acc wen t ws t wh t da dout[] t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t as a[] t ah (csn= low, oen = don? care) wen t ws t wh di[] t cyc ck t ckl t ckh a0 a2 a1 t ds t dh d0 d2 d1 t bws bwen[] t bwh bw0 bw2 bw1
std130 5-70 samsung asic dpsrambw_hd high-density dual-port synchronous static ram with bit-write read cycle with csn-controlled oen-controlled output enable contention mode note: ?on't care?means the condition that these pins are in normal operation mode. t as a[] t ah (oen = low, wen = high, di[], bwen[] = don? care) csn t cs t ch dout[] t cyc ck t ckl t ckh a0 a2 a1 t da t acc m[a1] m[a0] (csn, ck, a[], wen, di[], bwen[] = don? care) t od t dz hi-z valid oen dout[] hi-z t zd ck1 tcc ck2 (a1[] = a2[])
samsung asic 5-71 std130 sparam_hd high-density single-port asynchronous static ram logic symbol function description sparam_hd is a single-port asynchronous static ram which is provided as a compiler. sparam_hd is intended for use in high-density applications. at the falling edge of wen, the write cycle is initiated. at the rising edge of wen, the write cycle is ended. during the write cycle, the data on di[] is written into the memory location speci?d on a[]. the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay whenever a[] transition is detected. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. sparam_hd function table csn wen oen a di dout comment x x h x x z unconditional tri-state output h x l x x dout(t-1) de-selected (standby mode) l l valid valid dout(t-1) write cycle starts l l valid valid mem(a) write cycle ends and read cycle starts l l l stable valid dout(t-1) write cycle l h l toggle x mem(a) read cycle features suitable for high-density application separated data i/o asynchronous operation asynchronous tri-state output address transition detector write-enable transition detector chip-select transition detector bank-select transition detector automatic power-down mode available low noise output optimization zero standby current zero hold time for di flexible aspect ratio dual bank scheme available up to 512k bits capacity up to 32k number of words up to 128 number of bit per word csn wen oen a [m-1:0] di [b-1:0] sparam_hd_xmb dout [b-1:0] notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = ? log 2 w ? 4. banks(ba) is the number of banks.
std130 5-72 samsung asic sparam_hd high-density single-port asynchronous static ram parameter description sparam_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance unit: [sl] note: each pin? capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words(w) ba = 1 min 64 128 256 512 max 2048 4096 8192 16384 step 16 32 64 128 ba = 2 min 128 256 512 1024 max 4096 8192 16384 32768 step 32 64 128 256 bpw(b) min 1 1 1 1 max 128 64 32 16 step 1 1 1 1 name i/o description csn chip enable chip select input. the chip select signal acts as the memory enable signal for selections of multiple blocks. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if low, a read or write access can occur. when csn falls, an access is initiated. wen read/write enable write enable input. the write enable signal selects the type of memory access. the high state for a read access and the low state for a write access. upon the rising edge of wen, a write access completed and a read access initiated. oen data output enable output enable input. the output enable signal controls the output drivers from driven to tri-state condition unconditionally. a [ ] address address input bus. a[] should be stable when wen is low. the address selects the location to be accessed. when the address changes, the transi- tion is detected and the internal clock pulse is generated. di [ ] data input data input bus. the data input is written to the accessed location when wen is low. dout [ ] data output data output bus. the data output is data stored in the accessed location dur- ing a read access. data output driver has tri-state logic. when oen is low, the driver drives a certain value. otherwise, data output keeps hi-z state. during a write access, data on dout is predictable. csn wen oen a di dout 4.1567 3.9632 3.9632 3.9632 3.1644 16.5880
samsung asic 5-73 std130 sparam_hd high-density single-port asynchronous static ram block diagrams sparam_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from sparam_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the top edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the top-edge, the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. <1-bank architecture> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vss vdd vdd vss vss vdd vdd vss a[m-1:0] wen oen csn dout[b-1:b/2] dout[b/2-1:0] di[b-1:b/2] di[b/2-1:0]
std130 5-74 samsung asic sparam_hd high-density single-port asynchronous static ram application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in sparam_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of sparam_hd. 4. avoiding short transition on the address bus in sparam_hd, rather than the write operation which is synchronously performed by wen signal, the read operation is asynchronously performed whenever the address transition is occurred. in this case, if the short transition on the address, called a skew, is happened, since sparam_hd recognizes the short address transition as the stable address transition and do perform a read operation. at that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. to prevent such fail, the stable address cycle time (tcyc) is required. the essential requirement to recognize valid address transition is that at least minimum address period should be equal or greater than tacc (access time). 5. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver vdd vss vdd vss vss vdd vdd vss vdd vss vss vdd a[m-1:0] wen oen csn dout[b-1:b/2] dout[b/2-1:0] di[b-1:b/2] di[b/2-1:0]
samsung asic 5-75 std130 sparam_hd high-density single-port asynchronous static ram characteristics de?ition for ac timing (ns) symbol description symbol description t cyc address cycle time t as address setup time t cas address setup time for csn rise t ah address hold time t wh wen hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t wen wen pulse width low t acc data access time for read cycle t wacc data access time for wen rise t da de-access time t wda de-access time for wen rise t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
std130 5-76 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 128 256 256 512 512 768 768 bpw 32 32 48 48 64 64 80 80 ba 12121212 timing (ns) t cyc 2.53 2.55 2.60 2.60 2.69 2.67 2.79 2.75 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.71 2.73 2.78 2.78 2.87 2.85 2.97 2.93 t ah 0.39 0.38 0.45 0.42 0.56 0.49 0.68 0.57 t wh 2.71 2.73 2.78 2.78 2.87 2.85 2.97 2.93 t ds 0.31 0.29 0.33 0.30 0.37 0.32 0.43 0.34 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.04 1.09 1.06 1.11 1.08 1.14 1.11 1.17 t wen 1.67 1.67 1.70 1.69 1.77 1.73 1.85 1.78 t acc 2.53 2.55 2.60 2.60 2.69 2.67 2.79 2.75 t da 2.25 2.28 2.32 2.33 2.41 2.40 2.51 2.48 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.86 0.91 0.88 0.94 0.90 0.96 0.93 0.99 t dz 0.38 0.38 0.41 0.41 0.44 0.44 0.47 0.47 t zd 0.26 0.26 0.30 0.30 0.33 0.33 0.36 0.36 t od 0.44 0.45 0.48 0.48 0.51 0.51 0.55 0.55 power ( w/mhz) power_read 98.59 96.80 135.96 131.05 181.51 169.54 234.70 214.91 power_write 138.80 133.21 211.54 193.33 322.35 273.68 455.01 370.13 power_standby 18.06 37.68 25.68 53.16 34.24 70.38 42.69 88.86 area ( m) width 574.72 654.20 773.00 895.36 971.28 1136.52 1166.42 1374.54 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
samsung asic 5-77 std130 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parametersy words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.90 2.83 3.06 2.95 3.23 3.06 3.36 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.07 3.01 3.24 3.13 3.41 3.24 3.54 t ah 0.80 0.65 1.01 0.77 1.22 0.89 1.24 t wh 3.07 3.01 3.24 3.13 3.41 3.24 3.54 t ds 0.48 0.36 0.60 0.42 0.72 0.47 0.73 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.13 1.20 1.16 1.24 1.18 1.28 1.35 t wen 1.93 1.83 2.09 1.91 2.25 1.99 2.35 t acc 2.90 2.83 3.06 2.95 3.23 3.06 3.36 t da 2.62 2.56 2.78 2.68 2.95 2.79 3.09 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.95 1.02 0.98 1.06 1.00 1.10 1.17 t dz 0.50 0.50 0.53 0.53 0.56 0.56 0.56 t zd 0.40 0.40 0.44 0.43 0.47 0.47 0.47 t od 0.58 0.59 0.62 0.62 0.66 0.65 0.66 power ( w/mhz) power_read 291.21 262.07 369.21 319.11 454.12 379.47 458.92 power_write 605.25 478.95 839.12 639.83 1113.90 823.84 1139.20 power_standby 51.16 107.74 60.97 129.61 70.78 152.40 179.14 area ( m) width 1361.57 1612.56 1556.71 1850.58 1751.85 2088.61 2094.89 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
std130 5-78 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 256 512 512 1024 1024 1536 1536 bpw 16 16 24 24 32 32 40 40 ba 12121212 timing (ns) t cyc 2.52 2.54 2.58 2.59 2.67 2.65 2.76 2.72 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.70 2.72 2.76 2.76 2.85 2.83 2.94 2.90 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.70 2.72 2.76 2.76 2.85 2.83 2.94 2.90 t ds 0.34 0.32 0.35 0.32 0.40 0.34 0.46 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.03 1.08 1.04 1.09 1.06 1.11 1.07 1.14 t wen 1.69 1.70 1.73 1.71 1.80 1.75 1.88 1.80 t acc 2.52 2.54 2.58 2.59 2.67 2.65 2.76 2.72 t da 2.24 2.27 2.30 2.32 2.39 2.38 2.48 2.45 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.85 0.90 0.87 0.92 0.88 0.94 0.90 0.96 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.31 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 88.29 86.52 120.24 115.36 160.31 148.42 207.54 187.78 power_write 118.03 112.98 177.51 161.55 269.46 226.92 382.03 305.64 power_standby 12.26 25.48 16.87 34.45 22.44 44.89 27.63 55.88 area ( m) width 574.72 611.32 773.00 831.04 971.28 1050.76 1166.42 1267.34 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
samsung asic 5-79 std130 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.86 2.79 3.01 2.90 3.17 3.00 3.30 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.03 2.97 3.19 3.07 3.35 3.18 3.48 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.03 2.97 3.19 3.07 3.35 3.18 3.48 t ds 0.51 0.39 0.63 0.44 0.75 0.50 0.76 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.09 1.16 1.10 1.19 1.12 1.22 1.29 t wen 1.96 1.84 2.12 1.93 2.28 2.02 2.37 t acc 2.86 2.79 3.01 2.90 3.17 3.00 3.30 t da 2.57 2.52 2.73 2.63 2.89 2.73 3.03 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.91 0.98 0.93 1.01 0.94 1.04 1.11 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.37 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.57 0.57 0.57 power ( w/mhz) power_read 258.12 228.88 330.17 279.98 409.15 334.43 414.11 power_write 513.46 396.11 707.38 528.54 931.41 681.49 944.44 power_standby 32.84 67.11 39.39 80.35 45.96 94.07 114.26 area ( m) width 1361.57 1483.92 1556.71 1700.50 1751.85 1917.09 1923.37 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
std130 5-80 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 512 1024 1024 2048 2048 3072 3072 bpw 8 8 12 12 16 16 20 20 ba 12121212 timing (ns) t cyc 2.52 2.56 2.60 2.61 2.68 2.67 2.78 2.74 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.71 2.74 2.77 2.79 2.86 2.85 2.95 2.92 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.71 2.74 2.77 2.79 2.86 2.85 2.95 2.92 t ds 0.35 0.35 0.37 0.35 0.41 0.37 0.47 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.04 1.10 1.06 1.12 1.07 1.14 1.09 1.16 t wen 1.71 1.72 1.74 1.74 1.81 1.78 1.89 1.83 t acc 2.54 2.56 2.60 2.61 2.68 2.67 2.78 2.74 t da 2.26 2.29 2.32 2.34 2.40 2.40 2.50 2.47 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.87 0.92 0.88 0.94 0.89 0.96 0.91 0.98 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.32 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 84.60 82.81 114.65 109.77 152.82 140.94 198.11 178.35 power_write 105.74 100.94 157.78 141.64 239.54 198.20 340.56 269.54 power_standby 12.26 20.23 13.15 26.49 17.45 34.06 21.36 41.97 area ( m) width 574.72 589.88 773.00 789.88 971.28 1007.88 1166.42 1213.74 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
samsung asic 5-81 std130 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.87 2.81 3.03 2.92 3.18 3.03 3.32 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.05 2.99 3.20 3.10 3.36 3.20 3.50 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.05 2.99 3.20 3.10 3.36 3.20 3.50 t ds 0.52 0.42 0.64 0.47 0.76 0.53 0.79 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.10 1.18 1.12 1.21 1.13 1.24 1.31 t wen 1.97 1.87 2.13 1.96 2.30 2.05 2.40 t acc 2.87 2.81 3.03 2.92 3.18 3.03 3.32 t da 2.59 2.54 2.75 2.65 2.91 2.76 3.05 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.93 1.00 0.94 1.04 0.96 1.07 1.13 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.36 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.57 0.57 0.57 power ( w/mhz) power_read 246.74 217.48 316.91 266.62 394.04 319.12 399.09 power_write 458.86 349.81 634.87 468.92 838.44 605.40 845.82 power_standby 25.27 50.03 39.39 59.60 35.75 69.43 86.31 area ( m) width 1361.57 1419.60 1556.71 1625.46 1751.85 1831.33 1837.61 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
std130 5-82 samsung asic sparam_hd high-density single-port asynchronous static ram reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 2048 2048 4096 4096 6144 6144 bpw 4466881010 ba 12121212 timing (ns) t cyc 2.56 2.60 2.62 2.65 2.71 2.71 2.80 2.78 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.74 2.78 2.80 2.83 2.88 2.89 2.98 2.96 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.74 2.78 2.80 2.83 2.88 2.89 2.98 2.96 t ds 0.37 0.39 0.39 0.40 0.44 0.42 0.49 0.45 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.07 1.14 1.08 1.16 1.09 1.18 1.11 1.20 t wen 1.74 1.77 1.77 1.79 1.84 1.83 1.92 1.88 t acc 2.56 2.60 2.62 2.65 2.71 2.71 2.80 2.78 t da 2.28 2.34 2.34 2.38 2.43 2.45 2.52 2.52 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.89 0.96 0.90 0.98 0.92 1.00 0.93 1.02 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.32 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 82.70 80.93 111.84 106.98 149.12 137.24 193.44 173.68 power_write 99.72 95.05 147.99 133.66 224.67 186.56 319.08 252.24 power_standby 8.52 17.56 11.27 22.49 14.99 28.65 18.23 35.05 area ( m) width 574.72 579.16 773.00 782.80 971.28 986.44 1166.42 1186.94 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
samsung asic 5-83 std130 sparam_hd high-density single-port asynchronous static ram reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 8192 8192 12288 12288 16384 16384 32768 bpw 12 12 14 14 16 16 16 ba 1212122 timing (ns) t cyc 2.89 2.85 3.05 2.96 3.21 3.07 3.36 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.07 3.03 3.23 3.14 3.39 3.25 3.54 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.07 3.03 3.23 3.14 3.39 3.25 3.54 t ds 0.55 0.47 0.66 0.53 0.78 0.58 0.86 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.13 1.22 1.14 1.25 1.16 1.29 1.35 t wen 2.00 1.93 2.16 2.01 2.33 2.11 2.47 t acc 2.89 2.85 3.05 2.96 3.21 3.07 3.36 t da 2.61 2.59 2.77 2.69 2.93 2.80 3.10 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.95 1.05 0.97 1.08 0.98 1.11 1.17 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.36 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.58 0.57 0.57 power ( w/mhz) power_read 241.13 211.86 310.37 260.07 386.58 311.66 391.66 power_write 430.44 326.80 598.39 438.96 792.18 567.63 796.75 power_standby 21.50 41.55 26.10 49.32 30.74 57.24 72.46 area ( m) width 1361.57 1387.44 1556.71 1587.94 1751.85 1788.45 1794.73 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
std130 5-84 samsung asic sparam_hd high-density single-port asynchronous static ram timing diagrams read cycle read cycle with csn-controlled basic write cycle a[] (wen = high, csn = low, oen = low, di[] = don? care) t acc t da dout[] t cyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 a[] t acc t da dout[] t cyc valid m[a0] m[a2] a0 a1 a2 a3 t acc t da m[a1] t acc t da csn (oen = low, wen = high, di[] = don? care) t cas a[] t ah (csn = low, oen = don? care) wen t as t wen di[] a0 a1 a2 d1 d2 d0 t ds t dh t cyc
samsung asic 5-85 std130 sparam_hd high-density single-port asynchronous static ram write cycle with csn-controlled read-modi?d-write cycle notes: 1. when the wen hold time after the last address bit transition is satisfied, d+ will toggle in response to a successful read of the initial contents of address a1. when the wen hold time after the last address bit transition is not satisfied, d+ will go to unknown state. 2. address bits are not allowed to change while wen is low. if they do change, then the data for one or more addresses in the memory array may be corrupted. oen controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. a[] t ah (oen = don? care) wen t as t wen di[] a0 a1 a2 d1 d2 d0 t ds t dh csn t cs t ch t cyc a[] t acc t da dout[] t cyc m[a0] m[a2] a0 a1 a2 d+ t acc t wacc wen (csn = low, oen = low) di[] d1 d2 d0 t ds t dh t cyc t as t wen t ah d1 t da t wda t cyc (a[], wen, di[], csn = don? care) t od t dz hi-z valid oen dout[] hi-z t zd
std130 5-86 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write logic symbol function description sparambw_hd is a single-port synchronous static ram with bit-write capability which is provided as a compiler. sparambw_hd is intended for use in high-density applications. basically, its functionality is exactly same as sparam_hd except a bit-write operation which is controlled by bwen[], named bit-write enable signal bus. each bit of bwen[] enables or disable the write operation of its corresponding bit in di[]. at the falling edge of wen, the write cycle is initiated when csn is low. the data bytes or bits in di[], which their corresponding bit(s) in bwen[] are low, are written into the memory location speci?d on a[]. when all bits of bwen[] are high, any data in di[] are not written into the memory location speci?d on a[]. when all bits of bwen[] are low, the data in di[] are written into the memory location speci?d on a[], which is exactly same as the write operation in sparam_hd. at the rising edge of wen, th write cycle is ended. the read cycle is initiated when wen is high and csn is low. the data at dout[] become valid after a delay whenever a[] transition is detected. while in standby mode that csn is high, a[] and di[] are disabled, data stored in the memory is retained and dout[] remains stable. when oen is high, dout[] is placed in a high-impedance state. sparambw_hd function table csn wen oen a bwen di dout comment x x h x x x z unconditional tri-state output h x l x x x dout(t-1) de-selected (standby mode) l l valid all l valid dout(t-1) word-write cycle starts l l valid l valid dout(t-1) bit-write cycle starts l l valid all l valid mem(a) word-write cycle ends and read cycle starts l l valid l valid mem(a) bit-write cycle ends and read cycle starts l l l stable all l valid dout(t-1) word-write cycle l l l stable l valid dout(t-1) bit-write cycle l h l toggle x x mem(a) read cycle features suitable for high-density application bit-write capability separated data i/o asynchronous operation asynchronous tri-state output address transition detector write-enable transition detector chip-select transition detector bank-select transition detector automatic power-down mode available low noise output optimization zero standby current zero hold time for di and bwen flexible aspect ratio dual bank scheme available up to 512k bits capacity up to 32k number of words up to 128 number of bit per word csn wen bwen [b-1:0] a [m-1:0] di [b-1:0] sparambw_hd_xmb dout [b-1:0] notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = ? log 2 w ? 4. banks(ba) is the number of banks. oen
samsung asic 5-87 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write parameter description sparambw_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance unit: [sl] note: each pin? capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words(w) ba = 1 min 64 128 256 512 max 2048 4096 8192 16384 step 16 32 64 128 ba = 2 min 128 256 512 1024 max 4096 8192 16384 32768 step 32 64 128 256 bpw(b) min 1 1 1 1 max 128 64 32 16 step 1 1 1 1 name i/o description csn chip enable chip select input. the chip select signal acts as the memory enable signal for selec- tions of multiple blocks. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if low, a read or write access can occur. when csn falls, an access is ini- tiated. wen read/write enable write enable input. the write enable signal selects the type of memory access. the high state for a read access and the low state for a write access. upon the rising edge of wen, a write access completed and a read access initiated. bwen[ ] bit-write enable bit-write enable input bus. each bit of bwen[] enables/disables the write operation of corresponding data bit. bwen[i] corresponds to di[i] in bit-write. if wen and bwen[0] are low and bwen[1] is high, di[0] is written into the memory location speci?d on a[], but di[1] is not written. oen data output enable output enable input. the output enable signal controls the output drivers from driven to tri-state condition unconditionally. a [ ] address address input bus. a[] should be stable when wen is low. the address selects the location to be accessed. when the address changes, the transition is detected and the internal clock pulse is generated. di [ ] data input data input bus. the data input is written to the accessed location when wen is low. dout [ ] data output data output bus. the data output is data stored in the accessed location during a read access. data output driver has tri-state logic. when oen is low, the driver drives a certain value. otherwise, data output keeps hi-z state. during a write access, data on dout is predictable. csn wen bwen oen a di dout 4.1567 3.9632 3.1644 3.9632 3.9632 3.1644 16.5880
std130 5-88 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write block diagrams sparambw_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from sparambw_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the top edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the top-edge, the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. <1-bank architecture> ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver address & clock buffers i/o driver vss vdd vdd vss vss vdd vdd vss a[m-1:0] wen oen csn dout[b-1:b/2] dout[b/2-1:0] di[b-1:b/2] di[b/2-1:0] bwen[b-1:b/2] bwen[b/2-1:0]
samsung asic 5-89 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in sparambw_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of sparambw_hd. 4. avoiding short transition on the address bus in sparambw_hd, rather than the write operation which is synchronously performed by wen signal, the read operation is asynchronously performed whenever the address transition is occurred. in this case, if the short transition on the address, called a skew, is happened, since sparambw_hd recognizes the short address transition as the stable address transition and do perform a read operation. at that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. to prevent such fail, the stable address cycle time (tcyc) is required. the essential requirement to recognize valid address transition is that at least minimum address period should be equal or greater than tacc (access time). 5. a byte-write or word-write operation with sparambw_hd refer to the function table. in byte-write operation, the number of bwen[] signal bus should be divided by a byte (8) and eight bwen signals should be tied to a connection wire. in this case, di[] bus is controlled by a byte-wired bwen signal instead of each bwen bit. in word-write operation, the functionality is exactly same as sparam_hd. if all of bwen[] signal is tied to low state, di[] bus is only controlled by wen. <2-bank architecture > ram core word-line decoder x-dec word-line decoder ram core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. ram core word-line decoder x-dec word-line decoder ram core i/o driver address & clock buffers i/o driver vdd vss vdd vss vss vdd vdd vss vdd vss vss vdd a[m-1:0] wen oen csn dout[b-1:b/2] dout[b/2-1:0] di[b-1:b/2] di[b/2-1:0] bwen[b-1:b/2] bwen[b/2-1:0]
std130 5-90 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write 6. power reduction during standby mode. the standby power is measured on the condition that only csn is disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. characteristics de?ition for ac timing (ns) symbol description symbol description t cyc address cycle time t as address setup time t cas address setup time for csn rise t ah address hold time t bwh bwen hold time t bws bwen setup time t wh wen hold time t cs csn setup time t ch csn hold time t ds data-in setup time t dh data-in hold time t wen wen pulse width low t acc data access time for read cycle t wacc data access time for wen rise t da de-access time t wda de-access time for wen rise t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-91 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 128 256 256 512 512 768 768 bpw 32 32 48 48 64 64 80 80 ba 12121212 timing (ns) t cyc 2.53 2.55 2.60 2.60 2.69 2.67 2.79 2.75 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.71 2.73 2.78 2.78 2.87 2.85 2.97 2.93 t ah 0.39 0.38 0.45 0.42 0.56 0.49 0.68 0.57 t wh 2.71 2.73 2.78 2.78 2.87 2.85 2.97 2.93 t ds 0.31 0.29 0.33 0.30 0.37 0.32 0.43 0.34 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.04 1.09 1.06 1.11 1.08 1.14 1.11 1.17 t wen 1.67 1.67 1.70 1.69 1.77 1.73 1.85 1.78 t acc 2.53 2.55 2.60 2.60 2.69 2.67 2.79 2.75 t da 2.25 2.28 2.32 2.33 2.41 2.40 2.51 2.48 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.86 0.91 0.88 0.94 0.90 0.96 0.93 0.99 t dz 0.38 0.38 0.41 0.41 0.44 0.44 0.47 0.47 t zd 0.26 0.26 0.30 0.30 0.33 0.33 0.36 0.36 t od 0.44 0.45 0.48 0.48 0.51 0.51 0.55 0.55 power ( w/mhz) power_read 98.59 96.80 135.96 131.05 181.51 169.54 234.70 214.91 power_write 138.80 133.21 211.54 193.33 322.35 273.68 455.01 370.13 power_standby 18.06 37.68 25.68 53.16 34.24 70.38 42.69 88.86 area ( m) width 574.72 654.20 773.00 895.36 971.28 1136.52 1166.42 1374.54 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
std130 5-92 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parametersy words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.90 2.83 3.06 2.95 3.23 3.06 3.36 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.07 3.01 3.24 3.13 3.41 3.24 3.54 t ah 0.80 0.65 1.01 0.77 1.22 0.89 1.24 t wh 3.07 3.01 3.24 3.13 3.41 3.24 3.54 t ds 0.48 0.36 0.60 0.42 0.72 0.47 0.73 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.13 1.20 1.16 1.24 1.18 1.28 1.35 t wen 1.93 1.83 2.09 1.91 2.25 1.99 2.35 t acc 2.90 2.83 3.06 2.95 3.23 3.06 3.36 t da 2.62 2.56 2.78 2.68 2.95 2.79 3.09 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.95 1.02 0.98 1.06 1.00 1.10 1.17 t dz 0.50 0.50 0.53 0.53 0.56 0.56 0.56 t zd 0.40 0.40 0.44 0.43 0.47 0.47 0.47 t od 0.58 0.59 0.62 0.62 0.66 0.65 0.66 power ( w/mhz) power_read 291.21 262.07 369.21 319.11 454.12 379.47 458.92 power_write 605.25 478.95 839.12 639.83 1113.90 823.84 1139.20 power_standby 51.16 107.74 60.97 129.61 70.78 152.40 179.14 area ( m) width 1361.57 1612.56 1556.71 1850.58 1751.85 2088.61 2094.89 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
samsung asic 5-93 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 256 512 512 1024 1024 1536 1536 bpw 16 16 24 24 32 32 40 40 ba 12121212 timing (ns) t cyc 2.52 2.54 2.58 2.59 2.67 2.65 2.76 2.72 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.70 2.72 2.76 2.76 2.85 2.83 2.94 2.90 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.70 2.72 2.76 2.76 2.85 2.83 2.94 2.90 t ds 0.34 0.32 0.35 0.32 0.40 0.34 0.46 0.37 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.03 1.08 1.04 1.09 1.06 1.11 1.07 1.14 t wen 1.69 1.70 1.73 1.71 1.80 1.75 1.88 1.80 t acc 2.52 2.54 2.58 2.59 2.67 2.65 2.76 2.72 t da 2.24 2.27 2.30 2.32 2.39 2.38 2.48 2.45 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.85 0.90 0.87 0.92 0.88 0.94 0.90 0.96 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.31 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 88.29 86.52 120.24 115.36 160.31 148.42 207.54 187.78 power_write 118.03 112.98 177.51 161.55 269.46 226.92 382.03 305.64 power_standby 12.26 25.48 16.87 34.45 22.44 44.89 27.63 55.88 area ( m) width 574.72 611.32 773.00 831.04 971.28 1050.76 1166.42 1267.34 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
std130 5-94 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.86 2.79 3.01 2.90 3.17 3.00 3.30 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.03 2.97 3.19 3.07 3.35 3.18 3.48 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.03 2.97 3.19 3.07 3.35 3.18 3.48 t ds 0.51 0.39 0.63 0.44 0.75 0.50 0.76 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.09 1.16 1.10 1.19 1.12 1.22 1.29 t wen 1.96 1.84 2.12 1.93 2.28 2.02 2.37 t acc 2.86 2.79 3.01 2.90 3.17 3.00 3.30 t da 2.57 2.52 2.73 2.63 2.89 2.73 3.03 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.91 0.98 0.93 1.01 0.94 1.04 1.11 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.37 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.57 0.57 0.57 power ( w/mhz) power_read 258.12 228.88 330.17 279.98 409.15 334.43 414.11 power_write 513.46 396.11 707.38 528.54 931.41 681.49 944.44 power_standby 32.84 67.11 39.39 80.35 45.96 94.07 114.26 area ( m) width 1361.57 1483.92 1556.71 1700.50 1751.85 1917.09 1923.37 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
samsung asic 5-95 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 512 512 1024 1024 2048 2048 3072 3072 bpw 8 8 12 12 16 16 20 20 ba 12121212 timing (ns) t cyc 2.54 2.56 2.60 2.61 2.68 2.67 2.78 2.74 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.71 2.74 2.77 2.79 2.86 2.85 2.95 2.92 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.71 2.74 2.77 2.79 2.86 2.85 2.95 2.92 t ds 0.35 0.35 0.37 0.35 0.41 0.37 0.47 0.39 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.04 1.10 1.06 1.12 1.07 1.14 1.09 1.16 t wen 1.71 1.72 1.74 1.74 1.81 1.78 1.89 1.83 t acc 2.54 2.56 2.60 2.61 2.68 2.67 2.78 2.74 t da 2.26 2.29 2.32 2.34 2.40 2.40 2.50 2.47 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.87 0.92 0.88 0.94 0.89 0.96 0.91 0.98 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.32 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 84.60 82.81 114.65 109.77 152.82 140.94 198.11 178.35 power_write 105.74 100.94 157.78 141.64 239.54 198.20 340.56 269.54 power_standby 9.78 20.23 13.15 26.49 17.45 34.06 21.36 41.97 area ( m) width 574.72 589.88 773.00 798.88 971.28 1007.88 1166.42 1213.74 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
std130 5-96 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.87 2.81 3.03 2.92 3.18 3.03 3.32 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.05 2.99 3.20 3.10 3.36 3.20 3.50 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.05 2.99 3.20 3.10 3.36 3.20 3.50 t ds 0.52 0.42 0.64 0.47 0.76 0.53 0.79 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.10 1.18 1.12 1.21 1.13 1.24 1.31 t wen 1.97 1.87 2.13 1.96 2.30 2.05 2.40 t acc 2.87 2.81 3.03 2.92 3.18 3.03 3.32 t da 2.59 2.54 2.75 2.65 2.91 2.76 3.05 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.93 1.00 0.94 1.04 0.96 1.07 1.13 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.36 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.57 0.57 0.57 power ( w/mhz) power_read 246.74 217.48 316.91 266.62 394.04 319.12 399.09 power_write 458.86 349.81 634.87 468.92 838.44 605.40 845.82 power_standby 25.27 50.03 30.50 59.60 35.75 69.43 86.31 area ( m) width 1361.57 1419.60 1556.71 1625.46 1751.85 1831.33 1837.61 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
samsung asic 5-97 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 2048 2048 4096 4096 6144 6144 bpw 4466881010 ba 12121212 timing (ns) t cyc 2.56 2.60 2.62 2.65 2.71 2.71 2.80 2.78 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 2.74 2.78 2.80 2.83 2.88 2.89 2.98 2.96 t ah 0.40 0.39 0.47 0.44 0.57 0.50 0.70 0.59 t wh 2.74 2.78 2.80 2.83 2.88 2.89 2.98 2.96 t ds 0.37 0.39 0.39 0.40 0.44 0.42 0.49 0.45 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.07 1.14 1.08 1.16 1.09 1.18 1.11 1.20 t wen 1.74 1.77 1.77 1.79 1.84 1.83 1.92 1.88 t acc 2.56 2.60 2.62 2.65 2.71 2.71 2.80 2.78 t da 2.28 2.34 2.34 2.38 2.43 2.45 2.52 2.52 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.89 0.96 0.90 0.98 0.92 1.00 0.93 1.02 t dz 0.36 0.36 0.38 0.38 0.40 0.40 0.42 0.42 t zd 0.24 0.24 0.27 0.27 0.29 0.29 0.32 0.32 t od 0.43 0.43 0.45 0.45 0.47 0.47 0.50 0.50 power ( w/mhz) power_read 82.70 80.93 111.84 106.98 149.12 137.24 193.44 173.68 power_write 99.72 95.05 147.99 133.66 224.67 186.56 319.08 252.24 power_standby 8.52 17.56 11.27 22.49 14.99 28.65 18.23 35.05 area ( m) width 574.72 579.16 773.00 782.80 971.28 986.44 1166.42 1186.94 height 203.34 337.54 250.50 384.70 344.82 479.02 439.14 573.34
std130 5-98 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write reference table * for ymux=32 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 8192 8192 12288 12288 16384 16384 32768 bpw 12 12 14 14 16 16 16 ba 1212122 timing (ns) t cyc 2.89 2.85 3.05 2.96 3.21 3.07 3.36 t as 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cas 3.07 3.03 3.23 3.14 3.39 3.25 3.54 t ah 0.82 0.67 1.03 0.79 1.24 0.91 1.27 t wh 3.07 3.03 3.23 3.14 3.39 3.25 3.54 t ds 0.55 0.47 0.66 0.53 0.78 0.58 0.86 t dh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bws 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t bwh 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t ch 1.13 1.22 1.14 1.25 1.16 1.29 1.35 t wen 2.00 1.93 2.16 2.01 2.33 2.11 2.47 t acc 2.89 2.85 3.05 2.96 3.21 3.07 3.36 t da 2.61 2.59 2.77 2.69 2.93 2.80 3.10 t wda 0.10 0.10 0.10 0.10 0.10 0.10 0.10 t wacc 0.95 1.05 0.97 1.08 0.98 1.11 1.17 t dz 0.45 0.45 0.47 0.47 0.49 0.49 0.49 t zd 0.34 0.34 0.36 0.36 0.39 0.39 0.39 t od 0.52 0.52 0.55 0.55 0.58 0.57 0.57 power ( w/mhz) power_read 241.13 211.86 310.37 260.07 386.58 311.66 391.66 power_write 430.44 326.80 598.39 438.96 792.18 567.63 796.75 power_standby 21.50 41.55 26.10 49.32 30.74 57.24 72.46 area ( m) width 1361.57 1387.44 1556.71 1587.94 1751.85 1788.45 1794.73 height 533.46 667.66 722.10 856.30 910.74 1044.94 1799.50
samsung asic 5-99 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write timing diagrams read cycle read cycle with csn-controlled basic write cycle a[] (wen = high, csn = low, oen = low, bwen[], di[] = don? care) t acc t da dout[] t cyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 a[] t acc t da dout[] t cyc valid m[a0] m[a2] a0 a1 a2 a3 t acc t da m[a1] t acc t da csn (oen = low, wen = high, bwen[], di[] = don? care) t cas a[] t ah (csn = low, oen = don? care) wen t as t wen di[] a0 a1 a2 d1 d2 d0 t ds t dh t cyc bwen[] bw0 bw1 bw2 t bwh t bws
std130 5-100 samsung asic sparambw_hd high-density single-port asynchronous static ram with bit-write write cycle with csn-controlled read-modi?d-write cycle notes: 1. when the wen hold time after the last address bit transition is satisfied, d+ will toggle in response to a successful read of the initial contents of address a1. when the wen hold time after the last address bit transition is not satisfied, d+ will go to unknown state. 2. address bits are not allowed to change while wen is low. if they do change, then the data for one or more addresses in the memory array may be corrupted. a[] t ah (oen = don? care) wen t as t wen di[] a0 a1 a2 d1 d2 d0 t ds t dh csn t cs t ch t cyc bwen t bwh t bws bw0 bw1 bw2 a[] t acc t da dout[] t cyc m[a0] m[a2] a0 a1 a2 d+ t acc t wacc wen (csn = low, oen = low) di[] d1 d2 d0 t ds t dh t cyc t as t wen t ah d1 t da t wda t cyc bwen[] bw0 bw1 bw2 t bws t bwh
samsung asic 5-101 std130 sparambw_hd high-density single-port asynchronous static ram with bit-write oen-controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. (a[], wen, di[], csn, bwen[] = don? care) t od t dz hi-z valid oen dout[] hi-z t zd
std130 5-102 samsung asic drom_hd high-density synchronous diffusion programmable rom logic symbol function description drom_hd is a synchronous diffusion programmable rom which is provided as a compiler. drom_hd is intended for use in high-density applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, dout[] remains stable. when oen is high, dout is placed in a high-impedance state. drom_hd function table ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) l l valid mem(a) read cycle features suitable for high-density applications low-average power operation diffusion-programmable code available synchronous operation duty-free clock cycle asynchronous tri-state output latched inputs and outputs automatic power-down mode available low noise output optimization zero standby current zero hold time flexible aspect ratio dual-bank scheme available up to 512k bits capacity up to 16k number of words up to 128 number of bits per word ck csn oen dout [b?:0] drom_hd_xmb a [m-1:0] notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = ? log 2 w ? 4. banks (ba) is the number of banks.
samsung asic 5-103 std130 drom_hd high-density synchronous diffusion programmable rom parameter description drom_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b) and column mux(y) and number of banks(ba). pin descriptions pin capacitance (unit = sl) note: each pin? capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 6.21 2.40 2.56 2.58 10.25 ba = 2 4.04 2.40 2.56 2.58 10.25
std130 5-104 samsung asic drom_hd high-density synchronous diffusion programmable rom block diagrams drom_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from drom_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the top edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the top-edge, the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. <1-bank architecture> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address & clock buffers output driver vss vdd vdd vss vss vdd vdd vss ck csn oen a[m-1:0] dout[b-1:b/2] dout[b/2-1:0]
samsung asic 5-105 std130 drom_hd high-density synchronous diffusion programmable rom application notes 1. permitting over-the-cell routing in chip-level layout, over-the-cell routing in drom_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of drom_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen tied to low. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address & clock buffers output driver vss vdd vdd vss vss vdd vss vdd vdd vss vss vdd ck csn oen dout[b-1:b/2] dout[b/2-1:0] a[m-1:0]
std130 5-106 samsung asic drom_hd high-density synchronous diffusion programmable rom characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid output de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-107 std130 drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 64 128 128 256 256 512 512 bpw 32 48 48 64 64 80 80 ba 1121212 timing (ns) t cyc 2.53 2.53 2.65 2.53 2.65 2.56 2.68 t ckl 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ckh 0.79 0.79 0.90 0.79 0.91 0.79 0.92 t as 0.25 0.24 0.57 0.24 0.57 0.25 0.59 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.68 1.74 1.90 1.78 1.96 1.81 2.04 t da 1.33 1.41 1.52 1.49 1.60 1.63 1.72 t dz 0.34 0.38 0.38 0.41 0.41 0.45 0.45 t zd 0.45 0.48 0.48 0.51 0.51 0.54 0.54 t od 0.49 0.52 0.52 0.55 0.55 0.58 0.58 power ( w/mhz) power_read 119.11 163.12 211.30 214.40 262.48 290.63 329.18 power_standby 21.83 24.07 63.67 27.35 68.64 32.70 76.10 area ( m) width 422.14 577.91 575.92 735.67 731.69 897.40 889.45 height 162.02 171.22 316.02 185.62 330.42 214.42 359.22
std130 5-108 samsung asic drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.64 2.73 2.78 2.81 2.95 2.91 3.19 t ckl 0.51 0.61 0.51 0.64 0.51 0.66 0.76 t ckh 0.79 0.94 0.79 0.96 0.79 0.98 1.06 t as 0.27 0.61 0.29 0.64 0.32 0.66 0.76 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.61 0.51 0.64 0.51 0.66 0.76 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.99 2.11 2.17 2.26 2.36 2.41 2.69 t da 1.78 1.88 1.95 2.02 2.13 2.17 2.41 t dz 0.49 0.49 0.52 0.52 0.56 0.56 0.56 t zd 0.58 0.58 0.61 0.61 0.65 0.65 0.65 t od 0.62 0.62 0.65 0.65 0.69 0.69 0.69 power ( w/mhz) power_read 387.68 425.39 495.65 515.91 614.02 613.67 748.98 power_standby 37.68 88.59 46.10 96.79 54.53 104.98 142.28 area ( m) width 1055.82 1051.18 1211.92 1207.28 1368.02 1363.38 1368.02 height 272.02 416.82 329.62 474.42 387.22 532.02 762.42
samsung asic 5-109 std130 drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 256 256 512 512 1024 1024 bpw 16 24 24 32 32 40 40 ba 1121212 timing (ns) t cyc 2.53 2.53 2.65 2.52 2.65 2.56 2.68 t ckl 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ckh 0.79 0.79 0.90 0.79 0.91 0.79 0.92 t as 0.25 0.24 0.57 0.24 0.57 0.25 0.59 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.71 1.76 1.95 1.80 2.01 1.84 2.09 t da 1.34 1.41 1.53 1.50 1.61 1.63 1.73 t dz 0.32 0.34 0.34 0.36 0.36 0.38 0.38 t zd 0.43 0.45 0.45 0.47 0.47 0.49 0.49 t od 0.47 0.49 0.49 0.51 0.51 0.53 0.53 power ( w/mhz) power_read 91.85 119.80 166.89 152.17 200.48 198.75 245.08 power_standby 20.78 22.46 60.41 25.18 64.21 29.98 70.60 area ( m) width 422.14 577.91 575.92 735.67 731.69 897.40 889.45 height 164.02 171.22 316.02 185.62 330.42 214.42 359.22
std130 5-110 samsung asic drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.64 2.73 2.78 2.81 2.95 2.91 3.19 t ckl 0.51 0.61 0.51 0.64 0.51 0.66 0.76 t ckh 0.79 0.94 0.79 0.96 0.79 0.98 1.06 t as 0.27 0.61 0.29 0.64 0.32 0.66 0.76 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.61 0.51 0.64 0.51 0.66 0.76 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.01 2.15 2.19 2.31 2.38 2.45 2.73 t da 1.78 1.89 1.96 2.03 2.14 2.18 2.42 t dz 0.41 0.41 0.43 0.43 0.46 0.46 0.46 t zd 0.51 0.51 0.53 0.53 0.56 0.56 0.56 t od 0.55 0.55 0.57 0.57 0.60 0.60 0.60 power ( w/mhz) power_read 256.85 304.64 322.46 360.88 393.59 420.89 512.91 power_standby 31.41 82.03 42.28 89.14 50.14 96.24 133.53 area ( m) width 1055.82 1051.18 1211.92 1207.28 1368.02 1363.38 1368.02 height 272.02 416.82 329.62 474.42 387.22 532.02 762.42
samsung asic 5-111 std130 drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 512 512 1024 1024 2048 2048 bpw 8 121216162020 ba 1121212 timing (ns) t cyc 2.53 2.53 2.65 2.53 2.65 2.56 2.68 t ckl 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ckh 0.79 0.79 0.90 0.79 0.91 0.79 0.92 t as 0.25 0.24 0.57 0.24 0.57 0.25 0.59 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.51 0.57 0.51 0.57 0.51 0.59 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.75 1.81 2.03 1.85 2.09 1.88 2.17 t da 1.35 1.42 1.54 1.51 1.62 1.64 1.74 t dz 0.30 0.32 0.32 0.33 0.33 0.35 0.35 t zd 0.42 0.43 0.43 0.44 0.44 0.46 0.46 t od 0.45 0.47 0.47 0.48 0.49 0.50 0.50 power ( w/mhz) power_read 78.41 98.41 145.16 121.33 170.02 153.02 202.12 power_standby 20.26 21.68 58.80 24.12 62.08 28.63 67.93 area ( m) width 422.14 577.91 575.92 735.67 731.69 897.40 889.45 height 164.02 171.22 316.02 185.62 330.42 214.42 359.22
std130 5-112 samsung asic drom_hd high-density synchronous diffusion programmable rom reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.64 2.73 2.73 2.81 2.81 2.91 3.19 t ckl 0.51 0.61 0.52 0.64 0.52 0.66 0.76 t ckh 0.79 0.94 0.79 0.96 0.79 0.98 1.06 t as 0.27 0.61 0.24 0.64 0.18 0.66 0.76 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.51 0.61 0.52 0.64 0.52 0.66 0.76 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.05 2.24 2.24 2.39 2.43 2.53 2.81 t da 1.79 1.90 1.97 2.05 2.15 2.20 2.44 t dz 0.37 0.37 0.39 0.39 0.40 0.40 0.40 t zd 0.47 0.47 0.49 0.49 0.51 0.51 0.51 t od 0.51 0.51 0.53 0.53 0.55 0.55 0.55 power ( w/mhz) power_read 191.69 244.80 236.14 283.91 283.69 325.05 395.20 power_standby 32.79 78.80 40.38 85.34 47.96 91.89 129.18 area ( m) width 1055.82 1051.18 1211.92 1207.28 1368.02 1363.38 1368.02 height 272.02 416.82 329.62 474.42 387.22 532.02 762.42
samsung asic 5-113 std130 drom_hd high-density synchronous diffusion programmable rom timing diagrams read cycle read cycle with csn controlled oen-controlled output enable note: ?on? care?means the condition that these pins are in normal operation mode. t as a[] t ah (csn, oen = low) t acc t da dout[] t cyc ck t ckl a0 a2 valid m[a0] m[a1] m[a2] a1 t ckh (oen = low) t ch t cs csn dout[] a1 a2 a0 a[] t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a, csn = don? care) t od t dz hi-z valid oen dout hi-z t zd
std130 5-114 samsung asic mrom_hd high-density synchronous metal-2 programmable rom logic symbol function description mrom_hd is a synchronous metal-2 programmable rom which is provided as a compiler. mrom_hd is intended for use in high-density applications. the read cycle is initiated at the rising edge of ck. the data at dout[] become valid after a delay. while in standby mode that csn is high, dout[] remains stable. when oen is high, dout is placed in a high-impedance state. mrom_hd function table ck csn oen a dout comment x x h x z unconditional tri-state output x h l x dout(t-1) de-selected (standby mode) l l valid mem(a) read cycle features suitable for high-density applications low-average power/low-voltage operation metal2-programmable code available synchronous operation duty-free clock cycle asynchronous tri-state output latched inputs and outputs automatic power-down mode available low noise output optimization zero standby current zero hold time flexible aspect ratio dual-bank scheme available up to 512k bits capacity up to 16k number of words up to 128 number of bits per word ck csn oen dout [b?:0] mrom_hd_xmb a [m-1:0] notes: 1. words (w) is the number of words. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the column mux types. 5. m = ? log 2 w ? 4. banks (ba) is the number of banks.
samsung asic 5-115 std130 mrom_hd high-density synchronous metal-2 programmable rom parameter description mrom_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bits per word(b), column mux(y) and number of banks(ba). pin descriptions pin capacitance (unit = sl) note: each pin? capacitance is exactly same regardless of available mux types for same bank. parameters ymux = 8 ymux = 16 ymux = 32 words (w) ba = 1 min 64 128 256 max 2048 4096 8192 step 32 64 128 ba = 2 min 128 256 512 max 4096 8192 16384 step 64 128 256 bpw (b) min 2 2 2 max 128 64 32 step 1 1 1 name i/o description ck clock clock input. csn and a[] are latched into the rom on the rising edge of ck. if csn is low on the rising edge of ck, the rom is in read mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the rom on the rising edge of ck. when csn is low, the rom is enabled for reading. when csn is high, the rom goes to the standby mode and is disabled for reading. dout remains previous data output. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any inputs. when oen is high, dout is disabled and goes to high-impedance state. a [ ] address address input bus. the address is latched into the rom on the rising edge of ck. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the rom is in read mode. ck csn oen a dout ba = 1 5.94 1.76 1.97 1.76 7.84 ba = 2 3.24 1.76 1.97 1.76 7.84
std130 5-116 samsung asic mrom_hd high-density synchronous metal-2 programmable rom block diagrams mrom_hd has 2 different physical architectures due to the word depth. optionally, one of these architectures is generated from mrom_hd compiler. in dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. in 1-bank architecture, the power ports are located on the top-edge and the bottom edge of both right- and left-sides of the memory. in 2-bank architecture, the power ports are located on the top-edge, the middle-edge and the bottom-edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory regardless of architecture. <1-bank architecture> rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. output driver address & clock buffers output driver vss vdd vdd vss vss vdd vdd vss ck csn oen a[m-1:0] dout[b/2:b-1] dout[b/2-1:0]
samsung asic 5-117 std130 mrom_hd high-density synchronous metal-2 programmable rom application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in mrom_hd is permitted for only metal-5 and metal-6 layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of mrom_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is in disable mode and other signals are in operation mode except that oen is tied to low. if any of signals are actived while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode. <2-bank architecture > rom core word-line decoder x-dec word-line decoder rom core y-dec & sense amp. control block y-dec & sense amp. y-dec & sense amp. control block y-dec & sense amp. rom core word-line decoder x-dec word-line decoder rom core output driver address & clock buffers output driver vss vdd vdd vss vss vdd vss vdd vdd vss vss vdd ck csn oen dout[b/2:b-1] dout[b/2-1:0] a[m-1:0]
std130 5-118 samsung asic mrom_hd high-density synchronous metal-2 programmable rom characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t ch csn hold time from ck rise t ckl clock pulse width low t acc data access time t ckh clock pulse width high t da de-access time t as address setup time t dz dout drive to high-z time t ah address hold time t zd dout high-z to drive time t cs csn setup time t od oen to valid data output de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_standby the standby power consumption while csn is high, oen is low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-119 std130 mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 64 128 128 256 256 512 512 bpw 32 48 48 64 64 80 80 ba 1121212 timing (ns) t cyc 2.61 2.61 2.71 2.61 2.71 2.68 1.79 t ckl 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ckh 0.79 0.79 0.91 0.79 0.91 0.79 0.91 t as 0.34 0.34 0.62 0.33 0.62 0.31 0.63 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.80 1.91 2.07 1.98 2.17 2.05 2.27 t da 1.43 1.55 1.66 1.68 1.78 1.85 1.93 t dz 0.36 0.40 0.40 0.44 0.44 0.48 0.48 t zd 0.47 0.50 0.50 0.54 0.54 0.58 0.58 t od 0.50 0.54 0.54 0.58 0.58 0.62 0.62 power ( w/mhz) power_read 131.05 180.76 232.69 245.07 291.65 342.61 396.06 power_standby 25.98 28.48 72.90 31.88 78.23 37.11 85.77 area ( m) width 423.48 598.23 596.24 779.09 775.11 961.63 953.68 height 164.16 177.44 317.58 204.00 344.14 257.12 397.26
std130 5-120 samsung asic mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=8 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 1024 1024 1536 1536 2048 2048 4096 bpw 96 96 112 112 128 128 128 ba 1212122 timing (ns) t cyc 2.83 2.91 3.05 3.05 3.28 3.19 3.39 t ckl 0.63 0.64 0.63 0.65 0.63 0.67 0.72 t ckh 0.79 0.92 0.79 0.94 0.79 0.95 0.99 t as 0.26 0.64 0.25 0.65 0.23 0.67 0.72 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.64 0.63 0.65 0.63 0.67 0.72 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.28 2.37 2.52 2.57 2.75 2.75 3.03 t da 2.07 2.13 2.31 2.33 2.55 2.53 2.76 t dz 0.53 0.53 0.57 0.57 0.61 0.61 0.61 t zd 0.62 0.62 0.66 0.66 0.70 0.70 0.70 t od 0.66 0.66 0.70 0.70 0.74 0.74 0.74 power ( w/mhz) power_read 477.52 491.26 632.30 606.80 810.61 734.51 948.55 power_standby 41.53 97.70 48.76 105.14 55.99 112.58 141.78 area ( m) width 1136.41 1131.77 1308.86 1304.22 1481.32 1476.68 1481.32 height 363.36 503.50 469.60 609.74 575.84 715.98 1140.94
samsung asic 5-121 std130 mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 128 256 256 512 512 1024 1024 bpw 16 24 24 32 32 40 40 ba 1121212 timing (ns) t cyc 2.61 2.61 2.71 2.61 2.71 2.68 2.78 t ckl 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ckh 0.79 0.79 0.90 0.79 0.91 0.79 0.91 t as 0.34 0.34 0.62 0.33 0.62 0.31 0.63 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.83 1.93 2.12 2.01 2.21 2.07 2.31 t da 1.43 1.56 1.67 1.69 1.79 1.85 1.94 t dz 0.33 0.35 0.35 0.38 0.38 0.41 0.41 t zd 0.44 0.46 0.46 0.49 0.49 0.51 0.51 t od 0.48 0.50 0.50 0.53 0.53 0.55 0.55 power ( w/mhz) power_read 102.20 134.73 186.21 176.10 226.61 235.51 276.94 power_standby 24.90 26.84 69.59 29.69 73.80 34.38 80.26 area ( m) width 423.48 598.59 596.60 779.09 775.11 961.38 953.43 height 164.16 177.44 317.58 204.00 344.14 257.12 397.26
std130 5-122 samsung asic mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=16 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 2048 2048 3072 3072 4096 4096 8192 bpw 48 48 56 56 64 64 64 ba 1212122 timing (ns) t cyc 2.83 2.90 3.05 3.05 3.28 3.19 3.40 t ckl 0.63 0.64 0.63 0.65 0.63 0.67 0.72 t ckh 0.79 0.92 0.79 0.94 0.79 0.95 0.99 t as 0.26 0.64 0.25 0.65 0.23 0.67 0.72 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.64 0.63 0.65 0.63 0.67 0.72 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.30 2.42 2.54 2.61 2.78 2.80 3.07 t da 2.08 2.14 2.32 2.34 2.55 2.54 2.77 t dz 0.44 0.44 0.46 0.46 0.49 0.49 0.49 t zd 0.54 0.54 0.56 0.56 0.59 0.59 0.59 t od 0.58 0.58 0.60 0.60 0.63 0.63 0.63 power ( w/mhz) power_read 315.10 352.12 406.44 422.50 510.21 499.10 630.56 power_standby 38.23 91.12 44.92 97.46 51.60 103.80 133.03 area ( m) width 1136.24 1131.60 1308.78 130414 1481.32 1476.68 1481.32 height 363.36 503.50 469.60 609.74 575.84 715.98 1140.94
samsung asic 5-123 std130 mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 256 512 512 1024 1024 2048 2048 bpw 8 121216162020 ba 1121212 timing (ns) t cyc 2.61 2.61 2.71 2.61 2.71 2.67 2.77 t ckl 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ckh 0.79 0.79 0.91 0.79 0.91 0.79 0.91 t as 0.34 0.34 0.62 0.33 0.62 0.31 0.63 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.63 0.62 0.63 0.62 0.63 0.63 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 1.88 1.98 2.20 2.05 2.30 2.10 2.39 t da 1.44 1.57 1.68 1.70 1.80 1.86 1.95 t dz 0.31 0.33 0.33 0.35 0.35 0.37 0.37 t zd 0.42 0.44 0.44 0.46 0.46 0.48 0.48 t od 0.46 0.48 0.48 0.50 0.50 0.52 0.52 power ( w/mhz) power_read 87.98 112.37 163.66 141.91 193.97 181.95 230.55 power_standby 24.37 26.02 67.97 28.59 71.63 33.00 77.50 area ( m) width 423.48 599.50 597.51 779.09 775.11 960.84 952.89 height 164.16 177.44 317.58 204.00 344.14 257.12 397.26
std130 5-124 samsung asic mrom_hd high-density synchronous metal-2 programmable rom reference table * for ymux=32 (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: standby power is measured on the condition that other signals are in normal operation while csn is in disable mode and oen is low. parameters words 4096 4096 6144 6144 8192 8192 16384 bpw 24 24 28 28 32 32 32 ba 1212122 timing (ns) t cyc 2.82 2.90 3.05 3.04 3.28 3.19 3.40 t ckl 0.63 0.64 0.63 0.66 0.63 0.67 0.72 t ckh 0.79 0.92 0.79 0.94 0.79 0.95 0.99 t as 0.26 0.64 0.25 0.65 0.23 0.67 0.72 t ah 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t cs 0.63 0.64 0.63 0.65 0.63 0.67 0.72 t ch 0.01 0.01 0.01 0.01 0.01 0.01 0.01 t acc 2.34 2.50 2.58 2.70 2.82 2.88 3.15 t da 2.09 2.15 2.33 2.35 2.57 2.55 2.78 t dz 0.39 0.39 0.41 0.41 0.43 0.43 0.43 t zd 0.49 0.49 0.51 0.51 0.53 0.53 0.53 t od 0.53 0.53 0.55 0.55 0.57 0.57 0.57 power ( w/mhz) power_read 234.07 282.72 293.74 330.65 360.35 381.92 471.71 power_standby 36.59 87.79 43.00 93.61 49.42 99.41 128.69 area ( m) width 1135.88 1131.24 1308.60 1303.96 1481.32 1476.68 1481.32 height 363.36 503.50 469.60 609.74 575.84 715.98 1140.94
samsung asic 5-125 std130 mrom_hd high-density synchronous metal-2 programmable rom timing diagrams read cycle read cycle with csn controlled oen-controlled output enable note: ?on? care?means the condition that these pins are in normal operation mode. t as a[] t ah (csn, oen = low) t acc t da dout[] t cyc ck t ckl a0 a2 valid m[a0] m[a1] m[a2] a1 t ckh (oen = low) t ch t cs csn dout[] a1 a2 a0 a[] t as t ah m[a1] t acc t da ck t ckl t ckh t cyc m[a0] (ck, a, csn = don? care) t od t dz hi-z valid oen dout hi-z t zd
std130 5-126 samsung asic arfram_hd high-density multi-port asynchronous register file logic symbol function description arfram_hd is a multi-port asynchronous register ?e which is provided as a compiler. arfram_hd is intended for use in high-density applications. it allows maximum 4 ports with con?urable 1-to-2 read ports and 1-to-2 write ports. all read and write ports are fully independent. on the rising edge of ck, the write cycle is initiated when wen is low. while ck is high, the data at di[] is written into the memory location speci?d on wa[]. at the falling edge of ck, the write cycle is terminated. if wen is high, wa[] and di[] are disabled . it is called ?rite standby mode? when ren and oen are low, the data stored in the memory location speci?d on ra[] becomes valid through dout[] after a delay. if ren is high, ra[] is disabled and dout[] remains in the previous data output. it is called ?ead standby mode? when oen is high, dout[] is placed in a high-impedance state regardless of ren. arfram_hd function table ck wen wa di ra ren oen dout comment x h x x x x x x write standby mode l valid valid x x x x write cycle starts l x x x x x x write cycle ends xxxxxxh z unconditional tri-state output xxxxxhl dout(t-1) read standby mode xxxxt oggle l l mem(ra) read cycle xxxxv alid l mem(ra) read cycle with ren-controlled features high-density application suitable for high-speed application synchronous write operation asynchronous read operation fully independent port latched input and output separated data i/o flexible aspect ratio asynchronous tristate output zero standby current con?urable 1-to-2 read ports con?urable 1-to-2 write ports up to 16k bits capacity up to 1024k number of words up to 64 number of bits per word ck wa[m-1:0] ren dout[b?:0] arfram_hd_rw_xm ra[m-1:0] notes: 1. words(w) is the number of words. 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. 6. m = ? log 2 w ? 5. reads(nr) is the number of read ports(1-to-2). 4. writes(nw) is the number of write ports(1-to-2). wen di[b-1:0] oen
samsung asic 5-127 std130 arfram_hd high-density multi-port asynchronous register file parameter description arfram_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b), column mux(y), number of read ports(nr) and number of write ports(nw). pin descriptions parameters ymux(y) = 2 ymux(y) = 4 ymux(y) = 8 words (w) min 4 8 16 max 256 512 1024 step 2 4 8 bpw (b) min 1 1 1 max 64 32 16 step 1 1 1 write ports(nw) 1, 2 read ports(nr) 1, 2 name i/o description ck write clock write clock input on each write port. wen, wa[] and di[] are latched into the ram on the rising edge of ck. if wen is low on the rising edge of ck, the ram is in write mode. if wen is high on the rising edge of ck, the ram is in write standby mode. at the falling edge of ck, the write-operation completes and the ram is in a precharge state. wen write enable write enable input on each write port. wen is latched into the ram on the rising edge of ck. when wen is low, the write mode is enabled. when wen is high, it prevents the write-operation. it is called ?rite standby mode? wa [ ] write address write address bus on each write port. it speci?s the location in which the data will be written in the write-operation. wa[] is latched at the rising edge of ck. di [ ] data input data input bus on each write port. it contains data values to be written into the memory during the write-cycle. di[] is latched at the rising edge of ck. ren read enable read enable input on each read port. when ren is low, read is enabled. when ren is high, read is disabled and dout[] remains in the previous state. it is called ?ead standby mode oen data output enable output enable input on each read port. the low state enables output drivers and the high state disables output to go to the hi-z state. ra [ ] read address read address bus on each read port. it speci?s the location to be read in the read-operation. dout [ ] data output data output bus on each read port. when ren and oen are low, it presents the data word stored in the location speci?d by ra[]. when ren is high and oen is low, dout[] remains in the previous state. when oen is high, dout[] is in the high-impedance state regardless of ren.
std130 5-128 samsung asic arfram_hd high-density multi-port asynchronous register file pin capacitance (unit = sl) block diagrams arfram_hd supports only 1-bank architecture. the power ports are located on the top-edge and the bottom edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory. ck wen di ren oen wa ra dout 3.10 10.75 5.22 8.72 3.71 3.09 5.39 30.37 write decoder write buffer ram core read buffer read decoder write control block column mux read control block i/o driver vss vdd vdd vss vss vdd vdd vss dout[b-1:0] di[b-1:0] oen wen ra[m-1:0] ren ck wa[m-1:0]
samsung asic 5-129 std130 arfram_hd high-density multi-port asynchronous register file application notes 1. permitting over-the-cell routing. in arfram_hd, the over-the-cell routing is permitted for metal-4 or upper layers. namely, while doing layout on the chip-level, any signals to be routed can be crossed over the area of register ?e generated by arfram_hd compiler. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of arfram_hd. 4. contention mode under same addresses(ra[]=wa[] or wa0[] = wa1[]). in arfram_hd, simultaneous operations by both ports on the same address(ra[]=wa[] or wa0[] = wa1[]) such as read/write,write/read, write/write operation, cause a contention problem. simultaneous operations are de?ed as the state in which both ports are enabled and both address buses are equal. arfram_hd has no scheme preventing the contention mode. due to the simultaneous operations, silicon will behave unpredictably. a write operation cannot completes and data appearing at outputs may not be valid. please refer to the timing diagrams if you want to avoid the contention mode between both ports. 5. keeping the stable address cycle time in read mode. in arfram_hd, rather than the write operation which is synchronously performed by ck signal, the read operation is asynchronously performed whenever the address transition occures. so, in read mode if the another transition on the address occures after ?st transition within access time, read operation cannot completes. at that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. to prevent such fail, the stable read address cycle time (trcyc) is required. the essential requirement to recognize valid read address transition is that at least minimum address period should be equal or greater than tacc (access time). 6. power reduction during standby mode. arfram_hd provides two types of standby modes ?the write standby mode and the read standby mode. while in the write standby mode, wa[] and di[] except ck are blocked even though the transitions of those signals occure. while in the read standby mode, ra[] is blocked even though its transition occures. so, you can reduce the power consumption in arfram_hd by properly using two standby modes in your design.
std130 5-130 samsung asic arfram_hd high-density multi-port asynchronous register file characteristics de?ition for ac timing (ns) symbol description t wcyc miminum write clock cycle time for write cycle t ckl mimimum ck pulse width low to guarantee write cycle t ckh mimimum ck pulse width high to guarantee write cycle t was write address setup time from wa[] to ck rise t wah write address hold time from ck rise to wa[] t ws wen setup time from wen fall to ck rise t wh wen hold time from ck rise to wen rise t ds data-in setup time from di[] to ck rise t dh data-in hold time from ck rise to di[] t wwc write-write contention time from one ck to the other ck t wda de-access time from ck rise to dout t wacc data access time from ck fall t rcyc miminum ra[] cycle time for read cycle t acc data access time for read cycle t ras read address setup time from ra[] to ren rise t rah read address hold time from ren rise to ra[] t da de-access time from ra to dout t zd dout high-z to drive time t dz dout drive to high-z time t od oen to valid output time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_w_standby the write standby power consumption while wen is high and other signals are in normal operations. power_r_standby the read standby power consumption while ren is high, oen is low and other sig- nals are in normal operations. de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-131 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2(nr=1, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 32 64 128 256 bpw 8 163264 timing (ns) t wcyc 1.02 1.13 1.36 2.00 t ckl 0.66 0.65 0.63 0.69 t ckh 0.22 0.25 0.33 0.63 t was 0.43 0.40 0.36 0.33 t wah 0.01 0.01 0.01 0.01 t ws 0.71 0.69 0.67 0.70 t wh 0.30 0.30 0.30 0.30 t ds 0.50 0.48 0.43 0.40 t dh 0.01 0.01 0.01 0.01 t wda 1.29 1.44 1.57 1.78 t wacc 1.39 1.57 1.69 2.05 t rcyc 1.44 1.61 1.81 2.29 t acc 1.44 1.61 1.81 2.29 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.68 0.72 0.73 t zd 0.21 0.22 0.26 0.28 t dz 0.21 0.22 0.25 0.27 t od 0.41 0.44 0.48 0.60 power ( w/mhz) power_read 14.68 29.55 78.20 174.39 power_write 23.93 46.58 99.98 257.51 power_w_standby 1.59 2.39 3.90 6.95 power_r_standby 0.26 0.43 0.69 1.19 area ( m) width 174.54 256.82 408.58 708.18 height 217.48 297.80 473.40 824.60
std130 5-132 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4(nr=1, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t wcyc 1.02 1.13 1.34 1.94 t ckl 0.66 0.66 0.65 0.65 t ckh 0.22 0.24 0.32 0.61 t was 0.44 0.42 0.39 0.35 t wah 0.01 0.01 0.01 0.01 t ws 0.72 0.71 0.69 0.69 t wh 0.30 0.30 0.30 0.30 t ds 0.51 0.49 0.47 0.43 t dh 0.01 0.01 0.01 0.01 t wda 1.30 1.45 1.57 1.79 t wacc 1.40 1.58 1.70 2.06 t rcyc 1.45 1.62 1.82 2.31 t acc 1.45 1.62 1.82 2.31 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.67 0.70 0.71 t zd 0.20 0.21 0.24 0.25 t dz 0.20 0.21 0.23 0.25 t od 0.40 0.42 0.45 0.53 power ( w/mhz) power_read 12.79 25.31 69.17 154.65 power_write 25.23 46.03 95.82 242.87 power_w_standby 2.02 2.45 3.25 4.88 power_r_standby 0.37 0.58 0.79 1.24 area ( m) width 174.54 256.82 408.58 708.18 height 217.48 297.80 473.40 824.60
samsung asic 5-133 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8(nr=1, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t wcyc 1.04 1.13 1.34 1.91 t ckl 0.67 0.66 0.66 0.66 t ckh 0.23 0.23 0.30 0.57 t was 0.44 0.43 0.41 0.38 t wah 0.01 0.01 0.01 0.01 t ws 0.72 0.72 0.70 0.71 t wh 0.30 0.30 0.30 0.30 t ds 0.52 0.50 0.48 0.46 t dh 0.01 0.01 0.01 0.01 t wda 1.33 1.48 1.60 1.82 t wacc 1.42 1.60 1.72 2.09 t rcyc 1.47 1.64 1.84 2.33 t acc 1.47 1.64 1.84 2.33 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.68 0.70 0.71 t zd 0.20 0.21 0.23 0.25 t dz 0.20 0.21 0.22 0.24 t od 0.40 0.41 0.44 0.50 power ( w/mhz) power_read 12.16 23.41 65.03 144.19 power_write 27.86 47.98 96.95 239.34 power_w_standby 2.62 2.88 3.33 4.23 power_r_standby 0.49 0.72 0.94 1.45 area ( m) width 174.54 256.82 408.58 708.18 height 217.48 297.80 473.40 824.60
std130 5-134 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2(nr=1, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t wcyc 1.11 1.27 1.61 2.59 t ckl 0.36 0.37 0.52 1.09 t ckh 0.20 0.24 0.34 0.73 t was 0.55 0.52 0.48 0.43 t wah 0.01 0.01 0.01 0.01 t ws 0.84 0.83 0.82 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.63 0.60 0.55 0.51 t dh 0.01 0.01 0.01 0.01 t wwc 0.20 0.24 0.34 0.73 t wda 1.33 1.56 1.72 1.97 t wacc 1.35 1.57 1.71 2.01 t rcyc 1.44 1.61 1.81 2.29 t acc 1.44 1.61 1.81 2.29 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.68 0.72 0.73 t zd 0.21 0.22 0.26 0.28 t dz 0.21 0.22 0.25 0.27 t od 0.41 0.44 0.48 0.60 power ( w/mhz) power_read 14.68 29.55 78.20 174.39 power_write 24.92 52.72 120.13 366.81 power_w_standby 1.23 2.02 3.58 6.60 power_r_standby 0.26 0.43 0.69 1.19 area ( m) width 264.44 392.38 672.52 1088.62 height 208.86 297.80 469.42 824.78
samsung asic 5-135 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4(nr=1, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t wcyc 1.11 1.28 1.61 2.58 t ckl 0.37 0.37 0.52 1.09 t ckh 0.21 0.25 0.34 0.70 t was 0.56 0.54 0.51 0.47 t wah 0.01 0.01 0.01 0.01 t ws 0.85 0.84 0.84 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.63 0.62 0.59 0.55 t dh 0.01 0.01 0.01 0.01 t wwc 0.21 0.25 0.34 0.70 t wda 1.35 1.58 1.74 1.99 t wacc 1.37 1.58 1.73 2.03 t rcyc 1.45 1.62 1.82 2.31 t acc 1.45 1.62 1.82 2.31 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.67 0.70 0.71 t zd 0.20 0.21 0.24 0.25 t dz 0.20 0.21 0.23 0.25 t od 0.40 0.42 0.45 0.53 power ( w/mhz) power_read 12.79 25.31 69.17 154.65 power_write 25.97 52.60 117.15 369.39 power_w_standby 1.30 1.73 2.56 4.18 power_r_standby 0.37 0.58 0.79 1.24 area ( m) width 264.44 392.38 672.52 1088.62 height 208.86 297.80 469.42 824.78
std130 5-136 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8(nr=1, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t wcyc 1.14 1.27 1.62 2.59 t ckl 0.37 0.36 0.52 1.10 t ckh 0.23 0.25 0.34 0.68 t was 0.56 0.55 0.53 0.50 t wah 0.01 0.01 0.01 0.01 t ws 0.85 0.84 0.84 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.64 0.63 0.61 0.58 t dh 0.01 0.01 0.01 0.01 t wwc 0.23 0.25 0.34 0.68 t wda 1.39 1.62 1.77 2.03 t wacc 1.40 1.61 1.76 2.06 t rcyc 1.47 1.64 1.84 2.33 t acc 1.47 1.64 1.84 2.33 t ras 0.25 0.25 0.25 0.25 t rah 0.11 0.11 0.12 0.12 t da 0.66 0.68 0.70 0.71 t zd 0.20 0.21 0.23 0.25 t dz 0.20 0.21 0.22 0.24 t od 0.40 0.41 0.44 0.50 power ( w/mhz) power_read 12.16 23.41 65.03 145.19 power_write 28.53 50.52 116.46 369.94 power_w_standby 1.52 1.77 2.24 3.16 power_r_standby 0.49 0.72 0.94 1.45 area ( m) width 264.44 392.38 672.52 1088.62 height 208.86 297.80 469.42 824.78
samsung asic 5-137 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2(nr=2, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 32 64 128 256 bpw 8 163264 timing (ns) t wcyc 1.02 1.13 1.36 2.00 t ckl 0.66 0.65 0.63 0.69 t ckh 0.22 0.25 0.33 0.63 t was 0.43 0.40 0.36 0.33 t wah 0.01 0.01 0.01 0.01 t ws 0.71 0.69 0.67 0.70 t wh 0.30 0.30 0.30 0.30 t ds 0.50 0.48 0.43 0.40 t dh 0.01 0.01 0.01 0.01 t wda 1.29 1.44 1.57 1.78 t wacc 1.39 1.57 1.69 2.05 t rcyc 1.37 1.56 1.80 2.42 t acc 1.37 1.56 1.80 2.42 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.63 0.67 0.69 t zd 0.21 0.23 0.26 0.27 t dz 0.20 0.22 0.26 0.26 t od 0.37 0.41 0.49 0.69 power ( w/mhz) power_read 14.00 27.99 76.25 177.26 power_write 23.93 46.58 99.98 257.51 power_w_standby 1.59 2.39 3.90 6.95 power_r_standby 0.22 0.38 0.63 1.20 area ( m) width 252.61 377.28 597.42 1028.76 height 227.48 310.36 504.38 892.42
std130 5-138 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4(nr=2, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t wcyc 1.02 1.13 1.34 1.94 t ckl 0.66 0.66 0.65 0.65 t ckh 0.22 0.24 0.32 0.61 t was 0.44 0.42 0.39 0.35 t wah 0.01 0.01 0.01 0.01 t ws 0.72 0.71 0.69 0.69 t wh 0.30 0.30 0.30 0.30 t ds 0.51 0.49 0.47 0.43 t dh 0.01 0.01 0.01 0.01 t wda 1.30 1.45 1.57 1.79 t wacc 1.40 1.58 1.70 2.06 t rcyc 1.39 1.58 1.81 2.44 t acc 1.39 1.58 1.81 2.44 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.62 0.66 0.69 t zd 0.19 0.21 0.24 0.25 t dz 0.19 0.20 0.23 0.24 t od 0.35 0.38 0.43 0.56 power ( w/mhz) power_read 12.90 25.18 69.71 160.76 power_write 25.23 46.03 95.82 242.87 power_w_standby 2.02 2.45 3.25 4.88 power_r_standby 0.31 0.50 0.79 1.21 area ( m) width 252.61 377.28 597.42 1028.76 height 227.48 310.36 504.38 892.42
samsung asic 5-139 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8(nr=2, nw=1) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t wcyc 1.04 1.13 1.34 1.91 t ckl 0.67 0.66 0.66 0.66 t ckh 0.23 0.23 0.30 0.57 t was 0.44 0.43 0.41 0.38 t wah 0.01 0.01 0.01 0.01 t ws 0.72 0.72 0.70 0.71 t wh 0.30 0.30 0.30 0.30 t ds 0.52 0.50 0.48 0.46 t dh 0.01 0.01 0.01 0.01 t wda 1.33 1.48 1.60 1.82 t wacc 1.42 1.60 1.72 2.09 t rcyc 1.42 1.61 1.84 2.48 t acc 1.42 1.61 1.84 2.48 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.62 0.65 0.69 t zd 0.19 0.20 0.22 0.24 t dz 0.18 0.20 0.22 0.23 t od 0.35 0.36 0.40 0.49 power ( w/mhz) power_read 12.64 23.95 66.78 152.79 power_write 27.86 47.98 96.95 239.34 power_w_standby 2.62 2.88 3.33 4.23 power_r_standby 0.41 0.61 0.93 1.41 area ( m) width 252.61 377.28 597.42 1028.76 height 227.48 310.36 504.38 892.42
std130 5-140 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=2(nr=2, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 32 64 128 256 bpw 8 16 32 64 timing (ns) t wcyc 1.11 1.27 1.61 2.59 t ckl 0.36 0.37 0.52 1.09 t ckh 0.20 0.24 0.34 0.73 t was 0.55 0.52 0.48 0.43 t wah 0.01 0.01 0.01 0.01 t ws 0.84 0.83 0.82 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.63 0.60 0.55 0.51 t dh 0.01 0.01 0.01 0.01 t wwc 0.20 0.24 0.34 0.73 t wda 1.33 1.56 1.72 1.97 t wacc 1.35 1.57 1.71 2.01 t rcyc 1.37 1.56 1.80 2.42 t acc 1.37 1.56 1.80 2.42 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.62 0.67 0.69 t zd 0.21 0.23 0.26 0.27 t dz 0.20 0.22 0.26 0.26 t od 0.37 0.41 0.49 0.69 power ( w/mhz) power_read 14.00 27.99 76.25 177.26 power_write 24.92 52.6472 120.13 366.81 power_w_standby 1.23 2.02 3.58 6.60 power_r_standby 0.22 0.38 0.63 1.20 area ( m) width 314.59 468.34 736.90 1262.10 height 229.56 312.44 498.64 871.04
samsung asic 5-141 std130 arfram_hd high-density multi-port asynchronous register file reference table * for ymux=4(nr=2, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 64 128 256 512 bpw 4 8 16 32 timing (ns) t wcyc 1.11 1.28 1.61 2.58 t ckl 0.37 0.37 0.52 1.09 t ckh 0.21 0.25 0.34 0.70 t was 0.56 0.54 0.51 0.47 t wah 0.01 0.01 0.01 0.01 t ws 0.85 0.84 0.84 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.63 0.62 0.59 0.55 t dh 0.01 0.01 0.01 0.01 t wwc 0.21 0.25 0.34 0.70 t wda 1.35 1.58 1.74 1.99 t wacc 1.37 1.58 1.73 2.03 t rcyc 1.39 1.58 1.81 2.44 t acc 1.39 1.58 1.81 2.44 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.62 0.66 0.69 t zd 0.19 0.21 0.24 0.25 t dz 0.19 0.20 0.23 0.24 t od 0.35 0.38 0.43 0.56 power ( w/mhz) power_read 12.90 25.18 69.76 160.76 power_write 25.97 52.60 117.15 369.39 power_w_standby 1.30 1.73 2.56 4.18 power_r_standby 0.31 0.50 0.79 1.21 area ( m) width 314.59 468.34 736.90 1262.10 height 229.56 312.44 498.64 871.04
std130 5-142 samsung asic arfram_hd high-density multi-port asynchronous register file reference table * for ymux=8(nr=2, nw=2) (typical process, 1.8v, 25 c, output load=10sl, input slope=0.2 ns, sa=0.5) note: sl is a standard load and sa is an input switching activity ratio during a clock. parameters words 128 256 512 1024 bpw 2 4 8 16 timing (ns) t wcyc 1.14 1.27 1.62 2.59 t ckl 0.37 0.36 0.52 1.10 t ckh 0.23 0.25 0.34 0.68 t was 0.56 0.55 0.53 0.50 t wah 0.01 0.01 0.01 0.01 t ws 0.85 0.84 0.84 0.85 t wh 0.20 0.20 0.20 0.20 t ds 0.64 0.63 0.61 0.58 t dh 0.01 0.01 0.01 0.01 t wwc 0.23 0.25 0.34 0.68 t wda 1.39 1.62 1.77 2.03 t wacc 1.40 1.61 1.76 2.06 t rcyc 1.42 1.61 1.84 2.48 t acc 1.42 1.61 1.84 2.48 t ras 0.23 0.22 0.22 0.22 t rah 0.10 0.10 0.11 0.11 t da 0.60 0.62 0.65 0.69 t zd 0.19 0.20 0.22 0.24 t dz 0.18 0.20 0.22 0.23 t od 0.35 0.36 0.40 0.49 power ( w/mhz) power_read 12.64 23.95 66.78 152.79 power_write 28.53 50.52 116.46 369.94 power_w_standby 1.52 1.77 2.24 3.16 power_r_standby 0.41 0.61 0.93 1.41 area ( m) width 314.59 468.34 736.90 1262.10 height 229.56 312.44 498.64 871.04
samsung asic 5-143 std130 arfram_hd high-density multi-port asynchronous register file timing diagrams read cycle read cycle with ren-controlled write cycle ra[ ] (oen = low, ren= low, ck, wen, di[ ], wa[ ]= don? care) t acc t da dout[ ] t rcyc m[a0] m[a1] m[a2] m[a3] a0 a1 a2 a3 ra [ ] t acc t da dout [ ] t rcyc dout[t-1] a1 a2 t acc t da ren (oen = low, ck, wen, di[ ], wa[ ] = don? care) dout[a1] dout[a2] t ras t rah wa (ren, oen, ra[ ] = don? care) t ckl t ckh t wcyc t was t wah a1 di [ ] t ws t wh t ds t dh d1 d0 d2 a0 a2 ck wen
std130 5-144 samsung asic arfram_hd high-density multi-port asynchronous register file oen controlled output enable read-write contention note: if ck rise while wa[] is same as ra[], it is a read-write contention. while ck is high, dout[] is unknown and write data is valid. after twacc from the falling edge of ck, the read data (d1) is valid. (ck, ren, wen, di[ ], wa[ ], ra[ ] = don? care) t od t dz hi-z valid oen dout [ ] hi-z t zd ck< > (wa[ ] = ra[ ]; wen, ren, oen = low) wa[ ] a0 a1 a2 t ckl t ckh t wcyc t was t wah d0 d1 d2 t ds t dh a1 ra[ ] di [ ] m(a1) d1 t wda t wacc dout[ ]
samsung asic 5-145 std130 arfram_hd high-density multi-port asynchronous register file write-read contention note: while ck is high, if read access begins by ra<>[] which is same as wa<>[] latched at the rising edge of ck, it is write-read contention. the read data is invalid whereas the write is still valid. after twacc from the falling edge of ck, dout[] is valid. write-write contention notes: 1. if addresses latched at the rising edge of ck are same and t1 is smaller than or equal to twwc, it is write-write contention. the data stored at current address will be unpredictable. 2. "don't care" means the condition that these pins are in normal operation mode. ck< > (wa[ ] = ra[ ]; wen, ren, oen = low) wa< >[ ] a0 a1 a2 t ckl t ckh t wcyc t was t wah d0 d1 d2 t ds t dh m(a3) d1 t wda t wacc a3 dout< >[ ] ra< >[ ] di< >[ ] a1 ck0 (wa0[ ] = wa1[ ]; wen0, wen1 = low, oen, ren, ra[ ] = don? care) wa0[ ] a1 wa1[ ] di0 [ ] di1[ ] a3 d1 d2 a1 a2 d4 d5 a3 d3 t l a0 d0 ck1
std130 5-146 samsung asic fifo_hd high-density synchronous first-in first-out memory logic symbol function description fifo_hd is a synchronous ?st-in ?st-out buffer memory which is provided as a compiler. fifo_hd is intended for use in high-density applications. after valid reset, on the rising of wck, the write cycle is initiated when wen is low, rst is high and ff is low. the data on di[] is written into the memory location speci?d by the write pointer. during normal write operation, the rising edge of wck will reset ef if it is set. at the last available memory location, write operation will set ff. di[] and wen must satisfy the setup and hold requirements with respect to the rising edge of wck. on the rising edge of rck, the read cycle is initiated when ren is low, rst is high, rtm is high and ef is low. the data located in the memory speci?d by the read pointer comes in dout[] after some delay. during normal read operation, the rising edge of rck will reset ff if it is set. at the last available memory location with available data, read operation will set ef. a valid dout[] will be possibly in some speci?d time after the rising edge of rck, under that oen is low. and the output data will remain unchanged until the next read, reset, or retransmit mode come in. ren must satisfy the setup and hold requirements with respect to the rising edge of rck. when oen is high, dout[] is placed in a high-impedance state. in reset mode, a reset is globally initiated at the falling edge of rst. the reset operation will set ef and reset ff and make the data output zero.the reset operation will initiate the read pointer and the write pointer as 0. after reset operation, the status of ef will make rck inoperable. the valid write input signal will become operable as rst is high. the read input signal will remain inoperable until ef is reset by the ?st valid write. in retransmit mode, a retransmit is initiated at the falling edge of rtm only if the total number of writes after a reset operation is less than the word size of the memory in fifo_hd and more than 0 (0 < total number of write < w-1). the retransmit operation will initiate the read pointer as 0 to allow the retransmission of data, make dout[] zero and make ef reset if it is set. the valid read input signal will become operable as rtm is high. features suitable for high-density applications over-read and over-write protection capability retransmit capability synchronous operation duty-free clock cycle asynchronous tri-state output control latched full and empty status ?g output automatic power-down flexible aspect ratio up to 64k bits capacity up to 8k number of words up to 64 number of bits per word rck oen rtm ef fifo_hd_xm wen 1. words(w) is the number of words in fifo_hd 2. bpw(b) is the number of bits per word. 3. ymux(y) is one of the column mux types. ren rst wck notes: di[b-1:0] ff dout[b-1:0]
samsung asic 5-147 std130 fifo_hd high-density synchronous first-in first-out memory fifo_hd function table notes: 1. read is blocked when ren is high and the read port is in disable mode. 2. read is blocked when ef is high (overread protection). 3. under that oen is high, dout[] goes to tri-state output mode. 4. write is blocked when wen is high and the write port is in disable mode. 5. write is blocked when ff is high (overwrite protection). parameter description fifo_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w), number of bit per word(b) and column mux(y). rst wen wck ren rck rtm oem ef ff di dout comment x x xxxx x l reset mode hxxxx x x x l retransmit mode hx x l hll x dout(t) read mode hl xxxx l valid dout(t-1) write mode hx x l hl l x dout(t) read and empty mode hl xxxxl valid dout(t-1) write and full mode hx x h h l x x x dout(t-1) (note 1) hx x l h l h x x dout(t-1) (note 2) x x x x x x h x x x hi-z (note 3) hh xxxxxxv alid dout(t-1) (note 4) hl xxxxxhv alid dout(t-1) (note 5) parameters ymux(y) = 2 ymux(y) = 4 ymux(y) = 8 ymux(y) = 16 words (w) min 16 32 64 128 max 1024 2048 4096 8192 step w ? 128:16 w ? 256:32 w ? 512:64 w ? 1024:128 w > 128:128 w > 256:256 w > 512:512 w > 1024:1024 bpw (b) min 2 2 2 2 max 64 32 16 8 step 1 1 1 1
std130 5-148 samsung asic fifo_hd high-density synchronous first-in first-out memory pin descriptions name i/o description rck read clock read clock input. upon the rising edge of rck, it begins a read operation when ren is low, rst is high, rtm is high and ef is low. ren read enable read enable input. when ren is low, the read access occurs properly. conversely when ren is high, no read access can occur and the read port of the fifo_hd goes to power down mode. ren is latched at the rising edge of rck. oen data output enable output enable input. the data output enable is asynchronously operated regardless of the state of other inputs. when oen is high, dout is disabled and goes to high-impedance state. rst reset reset input. upon the falling edge of rst, the reset mode is initiated. rst resets the read and write pointer to their initial position. rst sets ef and resets ff. rst makes dout[] zero. rtm retransmit retransmit input. upon the falling edge of rtm, the retransmit mode is initiated, provided that rst is high. rtm resets the read pointer to its initial position. rtm makes dout[] zero. wck write clock write clock input. upon the rising edge of wck, it begins a write operation when we is low, rst is high and ff is low. wen write enable write enable input. when wen is low, a write access occurs properly. conversely when wen is high, no write access can occur and the write port of the fifo_hd goes to power down mode. wen is latched at the rising edge of wck. di data in data input bus. di[] is latched on the rising edge of wck. data input is written into the addressed location in write mode. ef empty flag empty flag. if the memory has no data to be read, ef goes high. valid reset makes ef high and valid retransmit makes it low. ff full flag full flag. if the memory has no vacancy to write data, ff goes high. valid reset makes ff low. dout data output data output bus. data output is valid after the rising edge of rck while the fifo_hd is in read mode when oen is low. conversely when oen is high, dout[] goes to high-impedance state. by reset or retransmit operation. dout[] goes to 0.
samsung asic 5-149 std130 fifo_hd high-density synchronous first-in first-out memory pin capacitance (unit = sl) block diagrams fifo_hd supports only 1-bank architecture. the power ports are located on the top-edge and the bottom edge of both right- and left-sides of the memory. all signal ports are only located on the bottom sides of the memory. rst rtm wck rck oen wen ren di dout 6.9826 3.0174 16.9246 9.4197 5.2998 3.4236 3.5010 2.538 7.6015 ram core write word-line shift register x-dec read word-line shift register ram core y-dec & sense amp. control block y-dec & sense amp. i/o driver clock buffers & flag generator i/o driver vss vdd vdd vss vss vdd vdd vss wen rst ff di1[b-1:b/2] dout1[b-1:b/2] dout1[b/2-1:0] di1[b/2-1:0] wck ef ren rck rtm oen
std130 5-150 samsung asic fifo_hd high-density synchronous first-in first-out memory application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in fifo_hd is permitted for metal-5 layer and metal-6 layer. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of fifo_hd. 4. fifo_hd must be reset before any operation performed. the reset operation initiates the read pointer and the write pointer as 0. 5. fifo_hd should be reset again before resuming normal operation if abnormal operation is performed. abnormal operations are invalid retransmit attemption, and read/write operation causing the timing requirement violations. 6. the retransmit operation initiates the read pointer as 0. 7. the retransmit is useful only when the total number of writes after a reset is less than the total word capacity of the fifo_hd and more than 0. 8. outputs are not changed until ?st valid read after a reset or retransmit.
samsung asic 5-151 std130 fifo_hd high-density synchronous first-in first-out memory characteristics de?ition for ac timing (ns) symbol description unit t rst min rst pulse width low ns t rtm min rtm pulse width low ns t rcyc read clock cycle time ns t rckh read clock pulse width high ns t rckl read clock pulse width low ns t wcyc write clock cycle time ns t wckh write clock pulse width high ns t wckl write clock pulse width low ns t rs ren setup to rck rising ns t rh ren hold from rck rising ns t ws wen setup to wck rising ns t wh wen hold from wck rising ns t wrcs wck setup to rck rising ns t rwcs rck setup to wck rising ns t ds di setup to wck rising ns t dh di hold from wck rising ns t rstw rst setup to wck rising ns t rtmr rtm setup to rck rising ns t rste delay from rst falling to ef rising ns t rstf delay from rst falling to ff falling ns t rstd delay from rst falling to dout zero ns t rstda output hold time from rst falling to dout ns t rtme delay from rtm falling to ef falling ns t rtmd delay from rtm falling to dout zero ns t rtmda output hold time from rtm falling to dout ns t we delay from wck rising to ef falling ns t wf delay from wck rising to ff rising ns t rf delay from rck rising to ff falling ns t re delay from rck rising to ef rising ns t acc data access time ns t da de-access time ns t dz dout drive to high-z time ns t zd dout high-z to drive time ns t od oen to valid output time ns de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle w/mhz power_write the dynamic average power consumption while in a write cycle w/mhz power_w_standby the write standby power consumption while wen is high w/mhz power_r_standby the read standby power consumption while ren is high w/mhz de?ition for area ( m) width the physical width in x-direction m height the physical height in y-direction m
std130 5-152 samsung asic fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=2 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 64 128 384 1024 bpw 16 32 48 64 timing (ns) t rst 3.13 3.13 3.14 3.63 t rtm 3.03 3.03 3.04 3.53 t rcyc 2.09 2.12 2.15 2.54 t rckl 0.48 0.48 0.48 0.48 t rckh 0.27 0.27 0.27 0.27 t wcyc 1.85 1.90 1.94 2.34 t wckl 0.59 0.61 0.64 0.67 t wckh 0.48 0.51 0.54 0.57 t rs 0.60 0.60 0.60 0.60 t rh 0.01 0.01 0.01 0.01 t ws 0.62 0.62 0.62 0.62 t wh 0.01 0.01 0.01 0.01 t ds 0.66 0.64 0.62 0.60 t dh 0.01 0.01 0.01 0.01 t rstw 0.36 0.36 0.36 0.36 t rtmr 0.36 0.36 0.36 0.36 t wrcs 0.94 0.94 0.94 0.94 t rwcs 1.02 1.02 1.02 1.40 t rstd 2.30 2.33 2.36 2.87 t rstda 0.43 0.45 0.47 0.48 t rste 3.08 3.08 3.09 3.58 t rstf 3.08 3.08 3.09 3.58 t rtmd 2.31 2.34 2.36 2.87 t rtmda 0.44 0.46 0.48 0.49 t rtme 2.85 2.85 2.86 3.35 t we 0.63 0.63 0.63 0.63 t wf 1.32 1.32 1.32 1.32 t re 1.27 1.27 1.27 1.27 t rf 0.68 0.68 0.68 0.68 t acc 1.69 1.72 1.75 2.14 t da 1.35 1.37 1.39 1.77 t dz 0.22 0.23 0.25 0.26 t zd 0.26 0.28 0.30 0.31 t od 0.44 0.47 0.49 0.51 power ( w/mhz) power_read 61.43 99.25 139.12 190.99 power_write 60.64 99.63 149.15 234.07 power_w_standby 3.15 5.70 8.19 10.73 power_r_standby 0.80 0.84 0.89 0.99 area ( m) width 459.54 632.34 805.14 977.94 height 242.08 288.16 476.68 947.98
samsung asic 5-153 std130 fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=4 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 128 256 768 2048 bpw 8 162432 timing (ns) t rst 3.13 3.13 3.14 3.63 t rtm 3.03 3.03 3.04 3.53 t rcyc 2.11 2.13 2.16 2.55 t rckl 0.48 0.48 0.48 0.48 t rckh 0.27 0.27 0.27 0.27 t wcyc 1.85 1.90 1.94 2.34 t wckl 0.58 0.60 0.62 0.64 t wckh 0.48 0.50 0.52 0.54 t rs 0.60 0.60 0.60 0.60 t rh 0.01 0.01 0.01 0.01 t ws 0.62 0.62 0.62 0.62 t wh 0.01 0.01 0.01 0.01 t ds 0.67 0.65 0.64 0.63 t dh 0.01 0.01 0.01 0.01 t rstw 0.36 0.36 0.36 0.36 t rtmr 0.36 0.36 0.36 0.36 t wrcs 0.94 0.94 0.94 0.94 t rwcs 1.02 1.02 1.03 1.40 t rstd 2.35 2.37 2.38 2.89 t rstda 0.42 0.44 0.45 0.46 t rste 3.08 3.08 3.09 3.58 t rstf 3.08 3.08 3.09 3.58 t rtmd 2.36 2.37 2.36 2.90 t rtmda 0.44 0.45 0.46 0.47 t rtme 2.85 2.85 2.86 3.35 t we 0.63 0.63 0.63 0.63 t wf 1.32 1.32 1.31 1.32 t re 1.27 1.27 1.27 1.27 t rf 0.68 0.68 0.68 0.68 t acc 1.71 1.73 1.76 2.15 t da 1.35 1.37 1.39 1.77 t dz 0.21 0.23 0.23 0.24 t zd 0.26 0.27 0.28 0.29 t od 0.43 0.45 0.47 0.48 power ( w/mhz) power_read 56.52 90.41 126.98 174.06 power_write 53.77 86.90 130.20 208.91 power_w_standby 1.91 3.25 4.49 5.77 power_r_standby 0.78 0.81 0.84 0.91 area ( m) width 459.54 632.34 805.14 977.94 height 242.08 288.16 476.68 947.98
std130 5-154 samsung asic fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=8 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) parameters words 256 512 1536 4096 bpw 4 8 12 16 timing (ns) t rst 3.13 3.13 3.14 3.63 t rtm 3.03 3.03 3.04 3.53 t rcyc 2.13 2.16 2.19 2.58 t rckl 0.48 0.48 0.48 0.48 t rckh 0.27 0.27 0.27 0.27 t wcyc 1.85 1.90 1.94 2.34 t wckl 0.57 0.59 0.60 0.62 t wckh 0.48 0.50 0.51 0.53 t rs 0.60 0.60 0.60 0.60 t rh 0.01 0.01 0.01 0.01 t ws 0.62 0.62 0.62 0.62 t wh 0.01 0.01 0.01 0.01 t ds 0.68 0.66 0.65 0.64 t dh 0.01 0.01 0.01 0.01 t rstw 0.36 0.36 0.36 0.36 t rtmr 0.36 0.36 0.36 0.36 t wrcs 0.94 0.94 0.94 0.94 t rwcs 1.02 1.02 1.02 1.40 t rstd 2.44 2.45 2.47 2.97 t rstda 0.42 0.43 0.44 0.45 t rste 3.08 3.08 3.09 3.58 t rstf 3.08 3.08 3.09 3.58 t rtmd 2.45 2.46 2.48 2.98 t rtmda 0.43 0.45 0.46 0.47 t rtme 2.85 2.85 2.86 3.35 t we 0.63 0.63 0.63 0.63 t wf 1.32 1.32 1.32 1.32 t re 1.27 1.27 1.27 1.27 t rf 0.68 0.68 0.68 0.68 t acc 1.73 1.76 1.79 2.18 t da 1.35 1.37 1.39 1.77 t dz 0.21 0.22 0.23 0.24 t zd 0.26 0.27 0.28 0.29 t od 0.43 0.45 0.46 0.47 power ( w/mhz) power_read 53.89 86.02 119.86 165.72 power_write 50.16 80.44 120.69 196.33 power_w_standby 1.26 2.00 2.64 3.29 power_r_standby 0.77 0.79 0.82 0.86 area ( m) width 459.54 632.34 805.14 977.94 height 242.08 288.16 476.68 947.98
samsung asic 5-155 std130 fifo_hd high-density synchronous first-in first-out memory reference table * for ymux=16 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa=0.5) parameters words 512 1024 3072 8192 bpw 2468 timing (ns) t rst 3.13 3.13 3.14 3.63 t rtm 3.03 3.03 3.04 3.53 t rcyc 2.18 2.20 2.23 2.62 t rckl 0.48 0.48 0.48 0.48 t rckh 0.27 0.27 0.27 0.27 t wcyc 1.86 1.90 1.94 2.34 t wckl 0.57 0.58 0.60 0.61 t wckh 0.50 0.51 0.53 0.54 t rs 0.60 0.60 0.60 0.60 t rh 0.01 0.01 0.01 0.01 t ws 0.62 0.62 0.62 0.62 t wh 0.01 0.01 0.01 0.01 t ds 0.68 0.66 0.65 0.65 t dh 0.01 0.01 0.01 0.01 t rstw 0.36 0.36 0.36 0.36 t rtmr 0.36 0.36 0.36 0.36 t wrcs 0.94 0.94 0.94 0.94 t rwcs 1.02 1.02 1.02 1.40 t rstd 2.62 2.63 2.64 3.15 t rstda 0.42 0.43 0.44 0.45 t rste 3.08 3.08 3.09 3.58 t rstf 3.08 3.08 3.09 3.58 t rtmd 2.63 2.64 2.65 3.16 t rtmda 0.43 0.44 0.45 0.46 t rtme 2.85 2.85 2.86 3.35 t we 0.63 0.63 0.63 0.63 t wf 1.32 1.32 1.32 1.32 t re 1.27 1.27 1.27 1.27 t rf 0.68 0.68 0.68 0.68 t acc 1.78 1.80 1.83 2.22 t da 1.36 1.37 1.39 1.77 t dz 0.21 0.22 0.23 0.23 t zd 0.26 0.27 0.27 0.28 t od 0.43 0.44 0.45 0.46 power ( w/mhz) power_read 52.35 83.71 116.62 161.43 power_write 47.58 77.30 116.00 190.23 power_w_standby 0.77 1.38 1.71 2.07 power_r_standby 0.77 0.77 0.80 0.85 area ( m) width 459.54 632.34 805.14 977.94 height 242.08 288.16 476.68 947.98
std130 5-156 samsung asic fifo_hd high-density synchronous first-in first-out memory timing diagrams normal read cycle notes: 1. read cycle is blocked during empty state (over-read protected) 2 .t wrcs is the timing related between first write on empty state and first subsequent read. if it is not satisfied, dout[i] will be unpredictable. 3. the is the timing related the read and empty mode. (rst, rtm = high, oen = low) t acc t da dout[i-1] dout[i] t rs t rh t rcyc rck t rckl t rckh t wrcs ren wck dout t rf ff t re ef
samsung asic 5-157 std130 fifo_hd high-density synchronous first-in first-out memory write cycle notes: 1. write cycle is blocked during full state (over-write protected) 2. t rwcs is the timing related between ?st read on full state and ?st subsequent write. if it is not satis?d, dout[i] (not shown) will be unpredictable. 3. t wf is the timing related the write and full mode. reset cycle note: read cycle and write cycle are blocked when rst is low. (rst = high) t dh di[i] t ws t wh t wcyc wck t wckl t wckh wen t we ef di[] t ds ff t rwcs t wf rck all 0s t rstw rst t rst wck, rck ff t rstf ef dout t rstda * note t rstd t rste
std130 5-158 samsung asic fifo_hd high-density synchronous first-in first-out memory retransmit cycle note: read cycle is blocked when rtm is low. oen controlled output enable all 0s t rtmr rtm t rst t rtme rck ef dout * note t rtmda t rtmd t od t dz hi-z valid oen dout [ ] hi-z t zd (ren = low)
samsung asic 5-159 std130 cam_hd high-density single-port synchronous binary cam logic symbol function description cam_hd is a single-port synchronous binary cam which is provided as a compiler. cam_hd is intended for use in high-density applications. on the rising edge of ck, the write cycle is initiated when wen is low and csn is low and cen and rn are high. the data on di[] is written to the addressed cam location and vdi overwrites the valid bit associated with cam entry with the state selected by a[], and dout[], vdo, cao[] and hit remains stable during a normal write access cycle. on the rising edge of ck, the read cycle begins when wen is high and csn is low and cen and rn are high. the data at dout[] become valid after a delay and vdo, during a normal read access cycle, reads back the valid bit associated with the a[] selected by cam entry. on the rising edge of ck, the compare cycle starts when csn and cen are low and rn are high, all valid data entries in the cam are simultaneously searched for the match pattern (cdi[]) de?ed by mask pattern(cmn[]). cdi[] bits are considered as matched bits at all times, if the corresponding bits of the applied cmn[] are in low states. each cam entry can be excluded from the compare function by setting the associated valid bit to a low state by the use of vdi. if one or more entries match with the masked cmn[] pattern, hit will be asserted and cao[] will contain the lowest one of all matched addresses by the built-in priority address encoder. while in standby mode that csn is high, data stored in the memory is retained and dout[], vdo, cao[] and hit remains stable. when oen is high, dout[] and vdo are placed in a high-impedance state. when aen is high, cao[] is placed in a high-impedance state. on the falling edge of rn, all the valid-bits are invalidated and settled to low states, therefore all the entries are excluded from cam match function so no match can occur. a low state of rn inhibits all access, same as when csn is in a high state. features suitable for high-density application separated data i/o synchronous operation duty-free clock cycle asynchronous tri-state output control latched inputs and outputs automatic power-down single cycle compare operation low noise output optimization global hit/miss built-in priority address encoder asynchronous reset control for all the valid-bits up to 32k bits capacity up to 512 number of words up to 64 number of bit per word ck oen aen dout[b-1:0] cam_hd_xm a[m-1:0] 1. words(w) is the number of words. 2. bpw(b) is the number of bits per word. 4. m = ? log 2 w ? wen cen cmn[b-1:0] notes: csn di[b-1:0] vdi cdi[b-1:0] rn vdo cao[m-1:0] hit 3. ymux(y) is one of the column mux types.
std130 5-160 samsung asic cam_hd high-density single-port synchronous binary cam cam_hd function table notes: 1. dout and vdo are high impedance when oen is high. 2. cao is high impedance when aen is high. 3. hit is 1 if matched or 0 if not. 4. match pattern is defined by cdi, bit-wise enabled by cmn. parameter description cam_hd is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; number of words(w) and number of bit per word(b) and column mux(y). ck csn rn wen aen oen a di/ vdi cdi cmn cen dout/ vdo hit cao comment x x l x l l x x x x x x x x reset x h h x l l x x x x x unch unch unch idle x x x x h h x x x x x z unch z tri-state l h l l l valid valid x x h unch unch unch write l h h l l valid x x x h data- out unch unch read l h x l l x x valid valid l unch 1 lowest of all matched addresses matched compare cycle l h x l l x x valid valid l unch 0 0 missed compare cycle parameters min max step note address inputs(m) 3 9 1 words(w) is limited to one of (8, 16, 32, 64, 128, 256, 512). words (w) 8 512 note bpw (b) 2 64 1 mux(y) 1 1 - capacity 16 32k -
samsung asic 5-161 std130 cam_hd high-density single-port synchronous binary cam pin descriptions name i/o description ck clock clock input. csn, wen, a[], di[], cdi[], cmn[], vdi and cen are latched into the ram on the rising edge of ck. if csn and wen are low and cen and rn are high on the rising edge of ck, the ram is in write mode. if csn is low and wen is high and cen and rn are high on the rising edge of ck, the ram is in read mode. if csn and cen are low and rn is high on the rising edge of ck, the ram is in compare mode. csn chip enable chip enable input. the chip enable is active-low and is latched into the ram on the rising edge of ck. when csn is low and rn is high, the ram is enabled for reading, writing or comparing, depending on the state of wen and cen. when csn is high and rn is high, the ram goes to the standby mode and is disabled for reading or writing or comparing. dout[], vdo, hit and cao[] remains previous data output. wen read/write enable read or write enable input. the read/write enable is latched into the ram on the rising edge of ck depending on the state of cen. when csn and wen is low and cen and rn are high, data are written to the addressed location and dout[], vdo, hit and cao[] remains stable. when csn is low and wen is high and cen and rn are high, data from the addressed word are present at dout[] and vdo, whereas hit and cao[] remains stable. oen data output enable data output enable input. the data output enable is asynchronously operated regardless of any input. when oen is high, dout[] and vdo are disabled and go to high-impedance state. cen compare enable compare enable input. the compare enable is latched into the ram on the rising edge of ck. when csn and cen is low and rn is high, the cam match function is activated. when csn is low and cen and rn are high, only read-write accesses are permitted. aen address output enable address output enable input. the address output enable is asynchronously operated regardless of any input. when aen is high, cao[] is disabled and goes to high-impedance state. cmn [ ] compare mask input compare mask input bus. cmn[] de?es the pattern which enables the cdi[] pattern to be used for the cam match function. if the cmn[] bit is low, the corresponding cdi[] bit will be interpreted as a wild card. a [ ] address address input bus. the address is latched into the ram on the rising edge of ck. di [ ] data input data input bus. data are latched on the rising edge of ck. data input is written into the addressed location in write mode. vdi valid bit input valid bit input. vdi overwrites the valid bit associated with the cam entry with the state selected by a[], during a normal write access cycle. valid bit input are latched on the rising edge of ck. cdi [ ] compare data input compare data input bus. compare-data are latched on the rising edge of ck and de?e the data pattern to be matched with the cam entries, in conjunction to cmn[]. rn reset enable reset enable. rn, if low, invalidates all the cam entries by setting all the valid-bits, one per entry, to low states, therefore all the entries are excluded from cam match function so no match can occur. a low state of rn inhibits all access, same as when csn is in a high state. dout [ ] data output data output bus. data output is valid after the rising edge of ck while the ram is in read mode. data output remains previous data output while the ram is in write mode and compare mode. vdo valid bit output valid bit output. vdo, during a normal read access cycle, reads back the valid bit associated with the a[] selected by cam entry. cao [ ] address output address output bus. cao[] presents the address of the matched entry, in a single match case. in a multiple-match case, cao[] is the lowest one of all matched addresses by the built-in priority address encoder. hit match output match output. hit indicates one or more cam entries matched the masked cdi[], if high.
std130 5-162 samsung asic cam_hd high-density single-port synchronous binary cam pin capacitance (unit = sl) block diagrams cam_hd supports only 1-bank architecture. the power ports are located on the top-edge and the bottom edge of both right- and left-sides of the memory. all signal ports except hit and cao are located on the bottom of the memory. hit and cao are located on the right-edge of the memory. ck csn wen oen cen aen cmn a 4.2847 0.7056 1.4209 0.7056 1.4209 1.5259 1.4209 1.4209 di vdi cdi rn dout cdo cao 1.4209 1.4209 1.4209 0.7056 16.7244 16.7244 16.7244 x-dec word-line decoder ram core priority address encoder i/o driver control block y-dec & sense amp. matched address control block address & clock buffers i/o driver vss vdd vdd vss vss vdd vdd vss oen cen vdo aen csn a[] wen vdi dout[] di[] cdi[] cmn[] rn ck hit cao[]
samsung asic 5-163 std130 cam_hd high-density single-port synchronous binary cam application notes 1. permitting over-the-cell routing. in chip-level layout, over-the-cell routing in cam_hd is permitted only for metal-5 layer or upper layers. 2. incoming power bus should be adjusted to guarantee not more than 10% voltage drop at typical-case current levels. 3. power stripe should be tapped from both sides of cam_hd. 4. power reduction during standby mode. the standby power is measured on the condition that only csn is disable mode and other signals are in operation mode. if any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in standby mode.
std130 5-164 samsung asic cam_hd high-density single-port synchronous binary cam characteristics de?ition for ac timing (ns) symbol description symbol description t cyc clock cycle time t da de-access time t ckl clock pulse width low t vdacc validity data access time t ckh clock pulse width high t vdda validity data de-access time t as address setup time t caacc matched address access time t ah address hold time t cada matched address de-access time t cs csn setup time t htacc global hit/miss access time t ch csn hold time t htda global hit/miss de-access time t ds data-in setup time t dz dout drive to high-z time t dh data-in hold time t zd dout high-z to drive time t ws wen setup time t od oen to valid output time t wh wen hold time t vddz vdo drive to high-z time t ces cen setup time t vdzd vdo high-z to drive time t ceh cen hold time t vdod oen to valid output time for vdo t cms cmn setup time t cadz cao drive to high-z time t cmh cmn hold time t cazd cao high-z to drive time t vds vdi setup time t caod aen to valid output time for cao t vdh vdi hold time t rn min rn pulse width low t cds cdi setup time t rns rn setup time t cdh cdi hold time t rnh rn hold time t acc data access time de?ition for power consumption ( w/mhz) power_read the dynamic average power consumption while in a read cycle power_write the dynamic average power consumption while in a write cycle power_compare the dynamic average power consumption while in a compare cycle power_reset the dynamic average power consumption while in a reset mode power_standby the standby power consumption while csn and rn are high, oen and aen are low and other signals are in normal operations de?ition for area ( m) width the physical width in x-direction height the physical height in y-direction
samsung asic 5-165 std130 cam_hd high-density single-port synchronous binary cam reference table * for ymux=1 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 16 32 64 128 256 512 bpw 8 8 8 8 8 8 timing (ns) t cyc 2.68 2.71 2.77 3.56 4.44 5.60 t ckl 0.70 0.72 0.74 0.75 0.77 0.78 t ckh 0.75 0.75 0.75 0.75 0.75 0.75 t as 0.25 0.25 0.25 0.25 0.25 0.25 t ah 0.25 0.28 0.30 0.32 0.35 0.37 t cs 0.70 0.72 0.74 0.75 0.77 0.78 t ch 0.50 0.50 0.50 0.50 0.50 0.50 t ces 0.38 0.40 0.42 0.43 0.45 0.45 t ceh 0.50 0.50 0.50 0.50 0.50 0.50 t cms 0.24 0.24 0.24 0.24 0.24 0.24 t cmh 0.30 0.30 0.30 0.30 0.30 0.30 t ds 0.24 0.24 0.24 0.24 0.24 0.24 t dh 0.33 0.33 0.33 0.33 0.33 0.33 t vds 0.24 0.24 0.24 0.24 0.24 0.24 t vdh 0.33 0.33 0.33 0.33 0.33 0.33 t cds 0.24 0.24 0.24 0.24 0.24 0.24 t cdh 0.30 0.30 0.30 0.30 0.30 0.30 t ws 0.19 0.19 0.19 0.19 0.19 0.19 t wh 0.25 0.28 0.30 0.32 0.35 0.37 t acc 1.41 1.45 1.52 1.64 1.88 2.40 t da 1.25 1.28 1.35 1.48 1.71 2.24 t dz 0.34 0.34 0.34 0.34 0.34 0.34 t zd 0.42 0.42 0.42 0.42 0.42 0.42 t od 0.46 0.46 0.46 0.46 0.46 0.46 t vdacc 1.41 1.45 1.52 1.64 1.88 2.40 t vdda 1.25 1.28 1.35 1.48 1.71 2.24 t vddz 0.34 0.34 0.34 0.34 0.34 0.34 t vdzd 0.42 0.42 0.42 0.42 0.42 0.42 t vdod 0.46 0.46 0.46 0.46 0.46 0.46 t caacc 2.04 2.13 2.37 2.85 3.52 4.35 t cada 1.26 1.31 1.39 1.77 2.20 2.76 t cadz 0.30 0.32 0.34 0.39 0.48 0.71 t cazd 0.41 0.43 0.45 0.50 0.59 0.83 t caod 0.46 0.47 0.50 0.54 0.64 0.87 t htacc 1.81 1.96 2.15 2.64 2.18 3.84 t htda 1.26 1.31 1.39 1.77 2.20 2.76 t rn 2.08 2.11 2.17 2.96 3.84 5.00 t rns 0.70 0.72 0.74 0.75 0.77 0.78 t rnh 2.08 2.11 2.17 2.96 3.84 5.00 power ( w/mhz) power_read 21.65 24.07 27.48 34.03 47.10 75.50 power_write 20.59 23.08 30.05 41.05 66.73 111.22 power_compare 81.76 92.65 111.20 145.38 196.97 306.16 power_standby 0.55 0.64 0.65 0.74 0.91 1.20 power_reset 1.37 2.23 3.74 7.21 15.85 39.82 area ( m) width 210.48 232.12 253.76 275.40 297.06 318.70 height 382.08 455.04 600.96 892.80 1476.48 2643.84
std130 5-166 samsung asic cam_hd high-density single-port synchronous binary cam reference table * for ymux=1 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 16 32 64 128 256 512 bpw 16 16 16 16 16 16 timing (ns) t cyc 2.84 2.87 2.94 3.71 4.59 5.66 t ckl 0.70 0.72 0.74 0.75 0.77 0.78 t ckh 0.75 0.75 0.75 0.75 0.75 0.75 t as 0.25 0.25 0.25 0.25 0.25 0.25 t ah 0.25 0.28 0.30 0.32 0.35 0.37 t cs 0.70 0.72 0.74 0.75 0.77 0.78 t ch 0.50 0.50 0.50 0.50 0.50 0.50 t ces 0.38 0.40 0.42 0.43 0.45 0.46 t ceh 0.50 0.50 0.50 0.50 0.50 0.50 t cms 0.24 0.24 0.24 0.24 0.24 0.24 t cmh 0.33 0.33 0.33 0.33 0.33 0.33 t ds 0.24 0.24 0.24 0.24 0.24 0.24 t dh 0.37 0.37 0.36 0.36 0.36 0.36 t vds 0.24 0.24 0.24 0.24 0.24 0.24 t vdh 0.37 0.37 0.36 0.36 0.36 0.36 t cds 0.24 0.24 0.24 0.24 0.24 0.24 t cdh 0.33 0.33 0.33 0.33 0.33 0.33 t ws 0.19 0.19 0.19 0.19 0.19 0.19 t wh 0.25 0.28 0.30 0.32 0.35 0.37 t acc 1.47 1.51 1.58 1.70 1.94 2.47 t da 1.31 1.34 1.41 1.54 1.78 2.30 t dz 0.37 0.37 0.37 0.37 0.37 0.37 t zd 0.45 0.45 0.45 0.45 0.45 0.45 t od 0.50 0.50 0.50 0.50 0.50 0.50 t vdacc 1.47 1.51 1.58 1.70 1.94 2.47 t vdda 1.31 1.34 1.41 1.54 1.78 2.30 t vddz 0.37 0.37 0.37 0.37 0.37 0.37 t vdzd 0.45 0.45 0.45 0.45 0.45 0.45 t vdod 0.50 0.50 0.50 0.50 0.50 0.50 t caacc 2.14 2.23 2.48 2.95 3.60 4.43 t cada 1.37 1.41 1.50 1.86 2.29 2.84 t cadz 0.30 0.32 0.34 0.39 0.48 0.71 t cazd 0.41 0.43 0.45 0.50 0.59 0.83 t caod 0.46 0.47 0.50 0.54 0.64 0.87 t htacc 1.92 2.07 2.26 2.73 3.26 3.92 t htda 1.37 1.41 1.50 1.86 2.29 2.84 t rn 2.24 2.27 2.34 3.11 3.99 5.06 t rns 0.70 0.72 0.74 0.75 0.77 0.78 t rnh 2.24 2.27 2.34 3.11 3.99 5.06 power ( w/mhz) power_read 30.19 33.11 37.06 43.98 58.04 88.70 power_write 28.21 32.54 41.53 56.73 89.40 152.97 power_compare 126.05 141.28 166.26 214.90 282.62 436.80 power_standby 0.67 0.79 0.83 0.98 1.19 1.69 power_reset 1.38 2.24 3.76 7.25 15.92 39.95 area ( m) width 255.44 277.08 298.72 320.36 342.02 363.66 height 382.08 455.04 600.96 892.80 1476.48 2643.84
samsung asic 5-167 std130 cam_hd high-density single-port synchronous binary cam reference table * for ymux=1 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 16 32 64 128 256 512 bpw 32 32 32 32 32 32 timing (ns) t cyc 3.13 3.16 3.23 4.01 4.86 5.88 t ckl 0.70 0.72 0.74 0.75 0.77 0.79 t ckh 0.75 0.75 0.75 0.75 0.75 0.75 t as 0.25 0.25 0.25 0.25 0.25 0.25 t ah 0.25 0.28 0.30 0.32 0.35 0.37 t cs 0.70 0.72 0.74 0.75 0.77 0.79 t ch 0.50 0.50 0.50 0.50 0.50 0.50 t ces 0.38 0.40 0.42 0.43 0.45 0.47 t ceh 0.50 0.50 0.50 0.50 0.50 0.50 t cms 0.24 0.24 0.24 0.24 0.24 0.24 t cmh 0.39 0.39 0.39 0.39 0.39 0.39 t ds 0.24 0.24 0.24 0.24 0.24 0.24 t dh 0.43 0.43 0.43 0.43 0.43 0.43 t vds 0.24 0.24 0.24 0.24 0.24 0.24 t vdh 0.43 0.43 0.43 0.43 0.43 0.43 t cds 0.24 0.24 0.24 0.24 0.24 0.24 t cdh 0.39 0.39 0.39 0.39 0.39 0.39 t ws 0.19 0.19 0.19 0.19 0.19 0.19 t wh 0.25 0.28 0.30 0.32 0.35 0.37 t acc 1.57 1.61 1.68 1.82 2.06 2.59 t da 1.41 1.45 1.52 1.65 1.89 2.42 t dz 0.43 0.43 0.43 0.43 0.43 0.43 t zd 0.51 0.51 0.51 0.51 0.51 0.51 t od 0.56 0.56 0.56 0.56 0.56 0.56 t vdacc 1.57 1.61 1.68 1.82 2.06 2.59 t vdda 1.41 1.45 1.52 1.65 1.89 2.42 t vddz 0.43 0.43 0.43 0.43 0.43 0.43 t vdzd 0.51 0.51 0.51 0.51 0.51 0.51 t vdod 0.56 0.56 0.56 0.56 0.56 0.56 t caacc 2.33 2.42 2.67 3.14 3.77 4.59 t cada 1.55 1.60 1.69 2.05 2.46 3.01 t cadz 0.30 0.32 0.34 0.39 0.48 0.71 t cazd 0.41 0.43 0.45 0.50 0.59 0.83 t caod 0.46 0.47 0.50 0.54 0.64 0.87 t htacc 2.10 2.26 2.45 2.92 3.43 4.08 t htda 1.55 1.60 1.69 2.05 2.46 3.01 t rn 2.53 2.56 2.63 3.41 4.26 5.28 t rns 0.70 0.72 0.74 0.75 0.77 0.79 t rnh 2.53 2.56 2.63 3.41 4.26 5.28 power ( w/mhz) power_read 48.19 52.48 63.38 65.01 81.08 116.12 power_write 44.04 50.60 57.26 88.61 141.73 237.62 power_compare 176.03 238.12 277.68 315.01 457.76 706.64 power_standby 0.96 1.09 1.15 1.38 1.78 2.52 power_reset 1.40 2.27 3.80 7.32 16.06 40.20 area ( m) width 345.36 367.00 388.64 410.28 431.94 453.58 height 382.08 455.04 600.96 892.80 1476.48 2643.84
std130 5-168 samsung asic cam_hd high-density single-port synchronous binary cam reference table * for ymux=1 (typical process, 1.8v, 25 c, output load = 10sl, input slope = 0.2 ns, sa = 0.5) parameters words 16 32 64 128 256 512 bpw 64 64 64 64 64 64 timing (ns) t cyc 3.68 3.72 3.79 4.58 5.43 6.42 t ckl 0.70 0.72 0.74 0.75 0.77 0.79 t ckh 0.75 0.75 0.75 0.75 0.75 0.75 t as 0.25 0.25 0.25 0.25 0.25 0.25 t ah 0.25 0.28 0.30 0.32 0.35 0.37 t cs 0.70 0.72 0.74 0.75 0.77 0.79 t ch 0.50 0.50 0.50 0.50 0.50 0.50 t ces 0.38 0.40 0.42 0.43 0.45 0.47 t ceh 0.50 0.50 0.50 0.50 0.50 0.50 t cms 0.24 0.24 0.24 0.24 0.24 0.24 t cmh 0.51 0.51 0.51 0.51 0.51 0.51 t ds 0.24 0.24 0.24 0.24 0.24 0.24 t dh 0.55 0.55 0.55 0.55 0.55 0.55 t vds 0.24 0.24 0.24 0.24 0.24 0.24 t vdh 0.55 0.55 0.55 0.55 0.55 0.55 t cds 0.24 0.24 0.24 0.24 0.24 0.24 t cdh 0.51 0.51 0.51 0.51 0.51 0.51 t ws 0.19 0.19 0.19 0.19 0.19 0.19 t wh 0.25 0.28 0.30 0.32 0.35 0.37 t acc 1.77 1.81 1.89 2.03 2.28 2.81 t da 1.60 1.64 1.72 1.86 2.12 2.65 t dz 0.55 0.55 0.55 0.55 0.55 0.55 t zd 0.62 0.62 0.62 0.62 0.62 0.62 t od 0.67 0.67 0.67 0.67 0.67 0.67 t vdacc 1.77 1.61 1.89 2.03 2.28 2.81 t vdda 1.60 1.64 1.72 1.86 2.12 2.65 t vddz 0.55 0.55 0.55 0.55 0.55 0.55 t vdzd 0.62 0.62 0.62 0.62 0.62 0.62 t vdod 0.67 0.67 0.67 0.67 0.67 0.67 t caacc 2.67 2.76 3.02 3.49 4.13 4.92 t cada 1.89 1.94 2.03 2.41 2.81 3.34 t cadz 0.30 0.32 0.34 0.39 0.48 0.71 t cazd 0.41 0.43 0.45 0.50 0.59 0.83 t caod 0.46 0.47 0.50 0.54 0.64 0.87 t htacc 2.44 2.60 2.80 3.28 3.78 4.49 t htda 1.89 1.94 2.03 2.41 2.81 3.34 t rn 3.08 3.12 3.19 3.98 4.83 5.82 t rns 0.70 0.72 0.74 0.75 0.77 0.79 t rnh 3.08 3.12 3.19 3.98 4.83 5.82 power ( w/mhz) power_read 86.85 93.50 100.12 110.23 130.68 174.62 power_write 89.99 90.01 111.90 157.16 244.13 411.65 power_compare 323.65 360.80 428.70 638.57 816.35 1241.60 power_standby 1.59 1.58 1.79 2.21 2.97 4.34 power_reset 1.50 2.32 3.88 7.46 16.33 40.71 area ( m) width 525.20 546.84 568.48 590.12 611.78 633.42 height 382.08 455.04 600.96 892.80 1476.48 2643.84
samsung asic 5-169 std130 cam_hd high-density single-port synchronous binary cam timing diagrams read cycle write cycle t as a t ah (rn=high, csn=low, oen=low, cen=high, aen, di, vdi, cdi, cmn= don? care) t acc wen t ws t wh t da dout/vdo t cyc ck t ckl t ckh a0 a2 valid m[a0] m[a1] m[a2] a1 t vdda t vdacc a (rn = high, csn = low, cen = high, oen, aen, cdi, cmn = don? care) t ckl t ckh t cyc t as t ah a1 di/vdi t ws t wh t ds t dh d1 d0 d2 a0 a2 ck wen t vds t vdh
std130 5-170 samsung asic cam_hd high-density single-port synchronous binary cam compare cycle csn controlled cmn (rn = high, csn = low, a, wen, oen, aen = don? care) t ckl t ckh t cyc t cms t cmh m1 cdi t ces t ceh t cds t cdh d1 d0 d2 m0 m2 ck cen t caacc unknown a(m[d1]) t htacc t htda t cada 00 hit cao miss cycle miss cycle hit cycle (rn, wen, oen cen, aen, a, di, vdi, cdi, cmn = valid) csn t cs t ch t cyc ck t ckl t ckh
samsung asic 5-171 std130 cam_hd high-density single-port synchronous binary cam oen/aen controlled output enable note: ?on't care?means the condition that these pins are in normal operation mode. rn controlled reset mode (rn, ck, csn, wen, cen, aen, cmn, a, di, vdi, cdi = don? care) t od t dz hi-z valid oen/aen dout/vdo/cao hi-z t zd t vdod t caod t vdzd t cazd t vddz t cadz rn (oen, csn, wen, cen, aen, cmn, a, di, vdi, cdi = valid) t ckl t ckh t cyc t rns t rnh t caacc/ t htacc valid ck dout/vdo t rn t acc/ t vdacc t da/ t vdda t cada/ t htda valid x x cao/hit

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